• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.463-463
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• 2012

ITRS (international technology roadmap for semiconductors)에 따르면 MOS(metal-oxide-semiconductor)의 CD (critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/$SiO_2$를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두된다고 보고하고 있다. 일반적으로 high-k dielectric를 식각시 anisotropic 한 식각 형상을 형성시키기 위해서 plasma를 이용한 RIE (reactive ion etching)를 사용하고 있지만 PIDs (plasma induced damages)의 하나인 PIED (plasma induced edge damage)의 발생이 문제가 되고 있다. PIED의 원인으로 plasma의 direct interaction을 발생시켜 gate oxide의 edge에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 high-k dielectric의 식각공정에 HDP (high density plasma)의 ICP (inductively coupled plasma) source를 이용한 원자층 식각 장비를 사용하여 PIED를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. One-monolayer 식각을 위한 1 cycle의 원자층 식각은 총 4 steps으로 구성 되어 있다. 첫 번째 step은 Langmuir isotherm에 의하여 표면에 highly reactant atoms이나 molecules을 chemically adsorption을 시킨다. 두 번째 step은 purge 시킨다. 세 번째 step은 ion source를 이용하여 발생시킨 Ar low energetic beam으로 표면에 chemically adsorbed compounds를 desorption 시킨다. 네 번째 step은 purge 시킨다. 결과적으로 self limited 한 식각이 이루어짐을 볼 수 있었다. 실제 공정을 MOS의 high-k dielectric에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU (North Carolina State University) CVC model로 구한 EOT (equivalent oxide thickness)는 변화가 없으면서 mos parameter인 Ion/Ioff ratio의 증가를 볼 수 있었다. 그 원인으로 XPS (X-ray photoelectron spectroscopy)로 gate oxide의 atomic percentage의 분석 결과 식각 중 발생하는 gate oxide의 edge에 trap의 감소로 기인함을 확인할 수 있었다.

• 전자공학회논문지D
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• 제36D권3호
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• pp.34-40
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• 1999

최근, 플라즈마 공정에 의해 발생하는 게이트 산화막의 손상은 게이트 산화막의 두께가 10nm이하로 감소함에 따라서 가정 중요한 신뢰성 문제들 중의 하나가 되고 있다. 플라즈마로 인한 손상은 metal 안테나 테스트 구조들을 가지고 연구되었다. Metal 안테나를 가지고 있는 NMOS에서 플라즈마로 인한 전하 축적으로 말미암아 10nm의 게이트 산화막에 전자 포획뿐만 아니라 정공 포획이 발생하는 것이 관측되었다. 정공포획은 전자 포획의 경우와 유사하게 transconductance(gm)의 감소를 일으키기는 하지만, 그 정도가 훨씬 적었다. 이는 플라즈마로 인한 축적이 정공 포획이 발생한 소자의 게이트 산화막에 가한 전기적 stress 가 전자 포획이 발생한 소자의 경우보다 훨씬 적었기 때문일 것이다. 이 이론은 산화막에서의 Fowler-Nordheim 전류 특성을 측정한 결과들에 의해 입증되었다.

• 센서학회지
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• 제15권2호
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• pp.90-96
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• 2006

We have fabricated the Pd-blck/NiCr gate MISFET-type $H_2$ sensor to detect the hydrogen in atmosphere. A differential pair-type structure was used to minimize the intrinsic voltage drift of the MISFET. The Pd-black film was deposited in the argon environment by thermal evaporation. In order to eliminate the blister formation in the surface of the hydrogen sensing gate metal, Pd-black/NiCr double metal layer was deposited on the gate insulator. The scanning electron microscopy and the auger electron spectroscopy was used to analyze their surface morphology and basic structure. The Pd-black/NiCr gate MISFET has been shown high sensitivity and stability more than Pd-planar/NiCr gate MISFET.

• 한국농공학회논문집
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• 제57권2호
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• pp.57-66
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• 2015

The purpose of this study was to improved the durability of a improved movable weir by replacing the improved movable weir's metal gate with a hybrid steel/glass fiber reinforced polymer composites panel gate. Because the metal gate of a improved movable weir is always in contact with water, its service life is shortened by corrosion. This study made four type of hybrid steel/glass fiber reinforced polymer composites panel gate with different steel gate surface deformation (control, sand blast, scratch and hole), flexural. Fracture properties tests were performed depending on the steel gate surface deformation. According to the test results, the flexural behavior, flexural strength and fracture properties of hybrid steel/glass fiber reinforced polymer composites panel gate was affected by the steel panel gate surface deformation. Also, the sand blast type hybrid steel/glass fiber reinforced polymer composites panel gate shows vastly superior flexural and fracture performance compared to other types.

• Advances in nano research
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• 제3권1호
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• pp.49-54
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• 2015

The structure represents symmetrical metal electrode (gate 1) - front $SiO_2$ layer - n-Si nanowire FET - buried $SiO_2$ layer - metal electrode (gate 2). At the symmetrical gate voltages high conductive regions near the gate 1 - front $SiO_2$ and gate 2 - buried $SiO_2$ interfaces correspondingly, and low conductive region in the central region of the NW are formed. Possibilities of applications of nanosize FETs at the deep inversion and depletion as a distributed capacitance are demonstrated. Capacity density is an order to ${\sim}{\mu}F/cm^2$. The charge density, it distribution and capacity value in the nanowire can be controlled by a small changes in the gate voltages. at the non-symmetrical gate voltages high conductive regions will move to corresponding interfaces and low conductive region will modulate non-symmetrically. In this case source-drain current of the FET will redistributed and change current way. This gives opportunity to investigate surface and bulk transport processes in the nanosize inversion channel.

• 전자공학회논문지D
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• 제35D권7호
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• pp.79-87
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• 1998

Nitrided oxides which have been investigated as alternative gate oxide for metal-oxide-semiconductor field effect devices were grown by two-step process using N$_{2}$O gas, and were chaacterized via a fowler-nordheim tunneling(FNT) electron injection technique. Electrical characteristics of nitrided gate oxides were superior to that of control oxides.Further, the FNT electron injection into the nitrided gate oxides reveals that gate oxides degrade more both if electrons were foreced to inject from the gate metal and if thicker nitrided gate oxides were used in the thickness range of 90~130.angs.. Models are suggested to explain these phenomena.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.104-104
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• 2009

Critical dimensions has rapidly shrunk to increase the degree of integration and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate insulator layer and the low conductivity characteristic of poly-silicon. To cover these faults, the study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$ and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-silicon gate is not compatible with high-k materials for gate-insulator. To integrate high-k gate dielectric materials in nano-scale devices, metal gate electrodes are expected to be used in the future. Currently, metal gate electrode materials like TiN, TaN, and WN are being widely studied for next-generation nano-scale devices. The TaN gate electrode for metal/high-k gate stack is compatible with high-k materials. According to this trend, the study about dry etching technology of the TaN film is needed. In this study, we investigated the etch mechanism of the TaN thin film in an inductively coupled plasma (ICP) system with $O_2/BCl_3/Ar$ gas chemistry. The etch rates and selectivities of TaN thin films were investigated in terms of the gas mixing ratio, the RF power, the DC-bias voltage, and the process pressure. The characteristics of the plasma were estimated using optical emission spectroscopy (OES). The surface reactions after etching were investigated using X-ray photoelectron spectroscopy (XPS) and auger electron spectroscopy (AES).

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권2호
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• pp.117-123
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• 2004

A 30 nm $In_{0.7}GaAs$ High Electron Mobility Transistor (HEMT) with triple-gate has been successfully fabricated using the $SiO_2/SiN_x$ sidewall process and BCB planarization. The sidewall gate process was used to obtain finer lines, and the width of the initial line could be lessened to half by this process. To fill the Schottky metal effectively to a narrow gate line after applying the developed sidewall process, the sputtered tungsten (W) metal was utilized instead of conventional e-beam evaporated metal. To reduce the parasitic capacitance through dielectric layers and the gate metal resistance ($R_g$), the etchedback BCB with a low dielectric constant was used as the supporting layer of a wide gate head, which also offered extremely low Rg of 1.7 Ohm for a total gate width ($W_g$) of 2x100m. The fabricated 30nm $In_{0.7}GaAs$ HEMTs showed $V_{th}$of -0.4V, $G_{m,max}$ of 1.7S/mm, and $f_T$ of 421GHz. These results indicate that InGaAs nano-HEMT with excellent device performance could be successfully fabricated through a reproducible and damage-free sidewall process without the aid of state-of-the-art lithography equipment. We also believe that the developed process will be directly applicable to the fabrication of deep sub-50nm InGaAs HEMTs if the initial line length can be reduced to below 50nm order.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.96-99
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• 2014

In high-${\kappa}$/metal-gate (HK/MG) metal-oxide-semiconductor field-effect transistors (MOSFETs) at 45-nm and below, the metal-gate material consists of a number of grains with different grain orientations. Thus, Monte Carlo (MC) simulation of the threshold voltage ($V_{TH}$) variation caused by the workfunction variation (WFV) using a limited number of samples (i.e., approximately a few hundreds of samples) would be misleading. It is ideal to run the MC simulation using a statistically significant number of samples (>~$10^6$); however, it is expensive in terms of the computing requirement for reasonably estimating the WFV-induced $V_{TH}$ variation in the HK/MG MOSFETs. In this work, a simple matrix model is suggested to implement a computing-inexpensive approach to estimate the WFV-induced $V_{TH}$ variation. The suggested model has been verified by experimental data, and the amount of WFV-induced $V_{TH}$ variation, as well as the $V_{TH}$ lowering is revealed.

• Transactions on Electrical and Electronic Materials
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• 제12권1호
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• pp.35-39
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• 2011

An electrically erasable programmable read-only memory (EEPROM) containing a stacked metal-insulator-metal (MIM) and n-well capacitor is proposed. It was fabricated using a 0.18 $\mu$m standard complementary metal-oxide semiconductor process. The depletion capacitance of the n-well region was effectively applied without sacrificing the cell-area and control gate coupling ratio. The device performed very similarly to the MIM capacitor cell regardless of the smaller cell area. This is attributed to the high control gate coupling ratio and capacitance. The erase speed of the proposed EEPROM was faster than that of the cell containing the MIM control gate.