• Journal of information and communication convergence engineering
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• 제10권2호
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• pp.200-204
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• 2012

This study has presented the analysis of breakdown voltage for a double-gate metal-oxide semiconductor field-effect transistor (MOSFET) based on the doping distribution of the Gaussian function. The double-gate MOSFET is a next generation transistor that shrinks the short channel effects of the nano-scaled CMOSFET. The degradation of breakdown voltage is a highly important short channel effect with threshold voltage roll-off and an increase in subthreshold swings. The analytical potential distribution derived from Poisson's equation and the Fulop's avalanche breakdown condition have been used to calculate the breakdown voltage of a double-gate MOSFET for the shape of the Gaussian doping distribution. This analytical potential model is in good agreement with the numerical model. Using this model, the breakdown voltage has been analyzed for channel length and doping concentration with parameters such as projected range and standard projected deviation of Gaussian function. As a result, since the breakdown voltage is greatly changed for the shape of the Gaussian function, the channel doping distribution of a double-gate MOSFET has to be carefully designed.

• 한국전기전자재료학회논문지
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• 제21권8호
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• pp.699-705
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• 2008

Capacitance versus voltage (C-V) characteristics of Ge-nanocrystal (NC)-embedded metal-oxide-semiconductor (MOS) capacitors with $HfO_2$ gate material were investigated in this work. The current versus voltage (I-V) curves obtained from Ge-NC-embedded MOS capacitors fabricated with the $NH_3$ annealed $HfO_2$ gate material reveal the reduction of leakage current, compared with those of MOS capacitors fabricated with the $O_2$ annealed $HfO_2$ gate material. The C-V curves of the Ge-NC-embedded MOS capacitor with $HfO_2$ gate material annealed in $NH_3$ ambient exhibit counterclockwise hysteresis loop of about 3.45 V memory window when bias voltage was varied from -10 to + 10 V. The observed hysteresis loop indicates the presence of charge storages in the Ge NCs caused by the Fowler-Nordheim (F-N) tunneling. In addition, capacitance versus time characteristics of Ge-NC-embedded MOS capacitors with $HfO_2$ gate material were analyzed to investigate their retention property.

• 한국방사선학회논문지
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• 제1권3호
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• pp.11-16
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• 2007

새로 개발된 몬테칼로 모사코드인 GATE의 방사선치료 분야에의 적용성 검토를 위하여 방사선치료 오차확인용 전자포탈영상장치에 사용되는 금속판/형광스크린 계측기의 특성을 예측 및 분석하였다. GATE를 이용하여 계산한 6 MV 선형가속기에서 발생되는 엑스선의 에너지 스펙트럼을 바탕으로, 여러가지 두께의 금속판/형광스크린에 대하여 계측효율과 공간분해능을 계산하였고, 이를 범용으로 사용되는 MCNP4B 모사 결과 및 실험 결과와 비교하여, 방사선치료 분야에 응용 가능성을 검증하였다.

• 한국전기전자재료학회논문지
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• 제35권3호
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• pp.255-263
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• 2022

The subthreshold swing (SS) of an asymmetric junctionless double gate (AJLDG) MOSFET is analyzed by the use of Gaussian function. In the asymmetric structure, the thickness of the top/bottom oxide film and the flat-band voltages of top gate (V_fbf) and bottom gate (V_fbb) could be made differently, so the change in the SS for these factors is analyzed with the projected range and standard projected deviation which are parameters for the Gaussian function. An analytical subthreshold swing model is presented from the Poisson's equation, and it is shown that this model is in a good agreement with the numerical model. As a result, the SS changes linearly according to the geometric mean of the top and bottom oxide film thicknesses, and if the projected range is less than half of the silicon thickness, the SS decreases as the top gate oxide film is smaller. Conversely, if the projected range is bigger than a half of the silicon thickness, the SS decreases as the bottom gate oxide film is smaller. In addition, the SS decreases as V_fbb-V_fbf increases when the projected range is near the top gate, and the SS decreases as V_fbb-V_fbf decreases when the projected range is near the bottom gate. It is necessary that one should pay attention to the selection of the top/bottom oxide thickness and the gate metal in order to reduce the SS when designing an AJLDG MOSFET.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.64-67
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• 2000

Tungsten silicide(WSi$_2$) is proposed for the alternate gate electrode of ULSI MOS devices. Good structural property and low resistivity of WSi$_2$ deposited by a low pressure chemical vapor deposition(LPCVD) method directly on SiO$_2$ is obtained after annealing. Especially, WSi$_2$-SiO2 interface remains flat after annealing tungsten silicide at high temperature. Electrical characteristics of annealed WSi$_2$-SiO$_2$-Si(MOS) capacitors were improved in view of charge trapping.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1990년도 추계학술대회 논문집 학회본부
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• pp.88-92
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• 1990

An accurate analytical threshold model is presented for fully depleted SOI which has a Metal-Insulator-Semiconductor-Insulator-Metal structure. The threshold voltage is defined as the gate voltage at which the second derivative of the inversion charge with respect to the gate voltage is maximum. Therefore the model is self-consistent with the measurement scheme. Numerical simulations show good agreement with the model with less than 3% error.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 A
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• pp.442-445
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• 1999

In this work, to detect of hydrogen in DI water in the generator area of nuclear power plants was fabricated Pd/Pt gate MISFET sensor using Pd membrane. $H_2$ permeation through Pd accounts for external mass transfer, surface adsorption and desorption, transitions to and from the bulk metal, and diffusion within the metal. The identification of pinholes in the generator area of plant is an important safety consideration, as hydrogen build-up gives rise to explosion. For this type of application the sensor needs to be isolated in DI water, accordingly, a Pd membrane was used to separate the DI water. The hydrogen in the DI water was then absorbed on the Pd thin film and diffused into the oil through the thin film. The Pd/Pt gate MISFET sensor, encapsulated by oil, will thereby detect permeated hydrogen.

• Design & Manufacturing
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• 제2권1호
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• pp.11-14
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• 2008

we can save a development cost and time as computer was used in tool and die design of car fields in die manufacture process. Dimension accuracy errors such as springback, springgo, overcrown and twist were reduced product accuracy and caused trouble to assembly each parts of car. In this paper, CADCEUS was used to modify and optimize results of deflection for a tail gate panel of car parts in order to reduce dimension accuracy errors by springback in sheet metal forming. As CADCEUS was used to apply for a tail gate panel, the time for quality to improve was reduced to 30%.

• 센서학회지
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• 제8권6호
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• pp.434-439
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• 1999

집적형 습도센서를 위해 이중게이트 금속을 증착한 차동형 전계효과 트랜지스터를 제조하고 상대습도에 따른 드레인전류 드리프트특성을 조사하였다. 감지소자와 비감지소자의 전류차를 얻기 위해 두 트랜지스터의 종횡비는 250/50으로 같게 하였다. 제조된 습도감지 전계효과 트랜지스터의 표준화된 드레인전류는 상대습도가 30%에서 90%로 증가함에 따라 0.12에서 0.3으로 증가하였다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 춘계 기술심포지움 논문집
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• pp.252-254
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• 2002

Metal oxides with high dielectric constants have the potential to expend scaling of transistor gate capacitance beyond that of ultrathin silicon dioxide. However, during deposition of most metal oxides on silicon, an interfacial region of SiOx is formed and limits the specific capacitance of the gate structure. We deposisted aluminum oxide and examined the composition of the interfacial layer by employing high-resolution X-ray photoelectron spectroscopy and X-ray reflectivity. We find that the interfacial region is not pure SiO$_2$, but is composed of a complex depth-dependent ternary oxide of $AlSi_xO_y$ and the pure SiO$_2$.