• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.8A
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• pp.706-711
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• 2012

Multi-level cell NAND flash is a flash memory technology using multiple levels per cell to allow more bits to be stored. Currently, most multi-level cell NAND stores 2 bits of information per cell. This reduces the amount of margin separating the states and results in the possibility of more errors. The most error cause is coupling noise. Thus, in this paper, we studied coupling noise cancellation scheme for reduction memory on the 16-level cell NAND flash memory channel. Also, we compared the performance threshold detection and proposed scheme.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.240-240
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• 2010

A multiple alloy metal nano-dots memory using FN tunneling was investigated in order to confirm its structural possibility for future flash memory. In this work, a multiple FePt nano-dots device with a high work function (~5.2 eV) and extremely high dot density (${\sim}\;1.2{\times}10^{13}/cm^2$) was fabricated. Its structural effect for multiple layers was evaluated and compared to one with a single layer in terms of the cell characteristics and reliability. We confirm that MOS capacitor structures with 2-4 multiple FePt nano-dot layers provide a larger threshold voltage window and better retention characteristics. Furthermore, it was also revealed that several process parameters for block oxide and inter-tunnel oxide between the nano-dot layers are very important to improve the efficiency of electron injection into multiple nano-dots. From these results, it is expected that a multiple FePt nano-dots memory using Fowler-Nordheim (FN)-tunneling could be a candidate structure for future flash memory.

• Journal of IKEEE
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• v.27 no.4
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• pp.386-390
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• 2023

In this study, we examined the quasi-nonvolatile memory characteristics of silicon nanosheet (SiNS) feedback field-effect transistors (FBFETs) fabricated using a complementary metal-oxide-semiconductor process. The SiNS channel layers fabricated by photoresist overexposure method had a width of approximately 180 nm and a height of 70 nm. The SiNS FBFETs operated in a positive feedback loop mechanism and exhibited an extremely low subthreshold swing of 1.1 mV/dec and a high ON/OFF current ratio of 2.4×10⁷. Moreover, SiNS FBFETs represented long retention time of 50 seconds, indicating the quasi-nonvolatile memory characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.43-54
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• 2007

This paper presents design and verification of a face detection hardware for real time application. Face detection algorithm detects rough face position based on already acquired feature parameter data. The hardware is composed of five main modules: Integral Image Calculator, Feature Coordinate Calculator, Feature Difference Calculator, Cascade Calculator, and Window Detection. It also includes on-chip Integral Image memory and Feature Parameter memory. The face detection hardware was verified by using S3C2440A CPU of Samsung Electronics, Virtex4LX100 FPGA of Xilinx, and a CCD Camera module. Our design uses 3,251 LUTs of Xilinx FPGA and takes about 1.96${\sim}$0.13 sec for face detection depending on sliding-window step size, when synthesized for Virtex4LX100 FPGA. When synthesized on Magnachip 0.25um ASIC library, it uses about 410,000 gates (Combinational area about 345,000 gates, Noncombinational area about 65,000 gates) and takes less than 0.5 sec for face realtime detection. This size and performance shows that it is adequate to use for embedded system applications. It has been fabricated as a real chip as a part of XF1201 chip and proven to work.

• Journal of the Korean Vacuum Society
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• v.18 no.4
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• pp.302-309
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• 2009

We fabricated a Si nano floating gate memory with Schottky barrier tunneling transistor structure. The device was consisted of Schottky barriers of Er-silicide at source/drain and Si nanoclusters in the gate stack formed by LPCVD-digital gas feeding method. Transistor operations due to the Schottky barrier tunneling were observed under small gate bias < 2V. The nonvolatile memory properties were investigated by measuring the threshold voltage shift along the gate bias voltage and time. We obtained the 10/50 mseconds for write/erase times and the memory window of $\sim5V$ under ${\pm}20\;V$ write/erase voltages. However, the memory window decreased to 0.4V after 104seconds, which was attributed to the Er-related defects in the tunneling oxide layer. Good write/erase endurance was maintained until $10^3$ write/erase times. However, the threshold voltages moved upward, and the memory window became small after more write/erase operations. Defects in the LPCVD control oxide were discussed for the endurance results. The experimental results point to the possibility of a Si nano floating gate memory with Schottky barrier tunneling transistor structure for Si nanoscale nonvolatile memory device.

• Journal of KIISE:Information Networking
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• v.31 no.1
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• pp.91-100
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• 2004

This paper presents a receiver-driven TCP flow control mechanism, which is adaptive to the wireless condition, for memory constrained mobile receiver. A receiver-driven TCP flow control is, in general, achieved by adjusting the size of advertised window at the receiver. The proposed method constantly measures at the receiver both the available wireless bandwidth and the packet round-trip time. Depending on the measured values, the receiver adjusts appropriately the size of advertised window. Constrained by the adjusted window which reflects the current state of the wireless network, the sender achieves an improved TCP throughput as well as the reduced round-trip packet delay. Its implementation only affects the protocol stack at the receiver and hence neither the sender nor the router are required to be modified. The mechanism has been implemented in real environments. The experimental results show that in CDMA2000 1x networks the TCP throughput of the proposed method has improved about 5 times over the conventional method when the receiver's buffer size is limited to 2896 bytes. Also, with 64Kbytes of buffer site, the packet round-trip time of the proposed method has been reduced in half, compared the case with the conventional method.

• The KIPS Transactions:PartD
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• v.11D no.5
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• pp.1003-1010
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• 2004

In this paper, we address efficient processing of subsequence matching in time-series databases. We first point out the performance problems occurring in the index searching of a prior method for subsequence matching. Then, we propose a new method that resolves these problems. Our method starts with viewing the index searching of subsequence matching from a new angle, thereby regarding it as a kind of a spatial-join called a window-join. For speeding up the window-join, our method builds an R＊-tree in main memory for f query sequence at starting of sub-sequence matching. Our method also includes a novel algorithm for joining effectively one R＊-tree in disk, which is for data sequences, and another R＊-tree in main memory, which is for a query sequence. This algorithm accesses each R＊-tree page built on data sequences exactly cure without incurring any index-level false alarms. Therefore, in terms of the number of disk accesses, the proposed algorithm proves to be optimal. Also, performance evaluation through extensive experiments shows the superiority of our method quantitatively.

• Journal of IKEEE
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• v.20 no.3
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• pp.273-278
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• 2016

In HEVC variable block size motion estimation, same search window data are duplicatedly used in each block size. It increases memory bandwidth, and it is difficult to exploit early termination. In this paper, largest block size and its corresponding smaller block sizes with same positions are performed at the same time. It reduces memory bandwidth and computation by reusing search window data and computation results. In the early termination, image quality can be degraded when it determines early termination by observing largest block size only, since smaller block sizes cannot be equally terminated due to their relative positions. So, in this paper, processing order of early termination is changed to perform smaller block sizes in turns. The designed motion estimation engine was described in Verilog HDL and it was synthesized and verified in 0.18um process technology. Its gate count and maximum operating frequency are 36,101 gates and 263.15 MHz, respectively.

• Transactions on Electrical and Electronic Materials
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• v.15 no.5
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• pp.241-244
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• 2014

Charge trap flash memory capacitors incorporating $(HfO_2)_x(Al_2O_3)_{1-x}$ film, as the charge trapping layer, were fabricated. The effects of the charge trapping layer composition on the memory characteristics were investigated. It is found that the memory window and charge retention performance can be improved by adding Al atoms into pure $HfO_2$; further, the memory capacitor with a $(HfO_2)_{0.9}(Al_2O_3)_{0.1}$ charge trapping layer exhibits optimized memory characteristics even at high temperatures. The results should be attributed to the large band offsets and minimum trap energy levels. Therefore, the $(HfO_2)_{0.9}(Al_2O_3)_{0.1}$ charge trapping layer may be useful in future nonvolatile flash memory device application.

• Fashion & Textile Research Journal
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• v.17 no.4
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• pp.501-512
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• 2015

This study was to consider and analyze of fashion window display design at Printemps department store in Paris, France which has tried continuously space presentations through the sensibility and differentiated strategy. The framework for analysis of this study was established by related precedent studies. Data collection was done by searching related specialty publications and website of Printemps department store, and the results of this study were drawn through qualitative analysis of experts' group. The results are as follows. Printemps department store set up presentation types of fashion window display design's themes that have been developed by the method of display presentation such as symbolic, ambience, surrealistic, realistic, and information. The most frequently used presentation development techniques applied in windows' VP of Printemps were the 'transferal of daily space', 'transferal of unexpected space', 'exaggeration of animal & plant', and 'descriptive narrative scene.' In addition, the display theme components such as the materials that can be easily accessible in everyday life, unique directing props, the memory or childhood, the image of animal or plant, and lighting etc. We found that the major colors of window display design at Printemps department store were purple, blue and black during the period from 2009 to 2014.