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A design and implementation of Face Detection hardware  

Lee, Su-Hyun (Dept of Electronics and Communication Engineering Kwangwoon University)
Jeong, Yong-Jin (Dept of Electronics and Communication Engineering Kwangwoon University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.44, no.4, 2007 , pp. 43-54 More about this Journal
Abstract
This paper presents design and verification of a face detection hardware for real time application. Face detection algorithm detects rough face position based on already acquired feature parameter data. The hardware is composed of five main modules: Integral Image Calculator, Feature Coordinate Calculator, Feature Difference Calculator, Cascade Calculator, and Window Detection. It also includes on-chip Integral Image memory and Feature Parameter memory. The face detection hardware was verified by using S3C2440A CPU of Samsung Electronics, Virtex4LX100 FPGA of Xilinx, and a CCD Camera module. Our design uses 3,251 LUTs of Xilinx FPGA and takes about 1.96${\sim}$0.13 sec for face detection depending on sliding-window step size, when synthesized for Virtex4LX100 FPGA. When synthesized on Magnachip 0.25um ASIC library, it uses about 410,000 gates (Combinational area about 345,000 gates, Noncombinational area about 65,000 gates) and takes less than 0.5 sec for face realtime detection. This size and performance shows that it is adequate to use for embedded system applications. It has been fabricated as a real chip as a part of XF1201 chip and proven to work.
Keywords
Face Detection; Integral Image; AdaBoost Cascade;
Citations & Related Records
Times Cited By KSCI : 4  (Citation Analysis)
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