• International Journal of Advanced Culture Technology
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• v.9 no.4
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• pp.282-287
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• 2021

A multicore system must be able to take full advantage of the program's instruction and data parallelism. This study introduces the data replication technique as a support technique to maximize the program's instruction and data parallelism. Instruction level parallelism can be limited by data dependency. In this case, if data is replicated to each processor core and used, instruction level parallelism can be used to the maximum. The technique proposed in this study can maximize the performance improvement effect when applied to scientific applications such as matrix multiplication operation.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.417-419
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• 2004

Because of the demands for high performance and high integrated system, the needs for optimal platform becomes more importance. Optimal platform can handle more data effectively with same resources. AMBA(Advanced Microprocessor Bus Architecture)$^{TM}$ defines on-chip communication standard for designing high performance embedded micro-controllers. It is consisted of AHB, ASB and APB. It can support fast implementation and reliability in system that is composed with reusable IPs. DMAC is one of master in system and generate master signals of AHB to communicate data from one slave(peripheral or memory) to another slave. It can reduce burden of CPU and increase system performance. We designed DMAC based on AMBA and it supports 13 Channels. Each channel can be controlled by software program. It decides channel's priority using round-robin method. It can support P2P, P2M, M2P and P2P communication.

• International Journal of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.9-17
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• 2017

This paper describes a process of developing commercial real time image recognition system with company. In this paper we will make a system that is combining an empirical kernel map method and conjugate least squares support vector machine in order to represent images in a low-dimensional subspace for real time image recognition. In the traditional approach calculating these eigenspace models, known as traditional PCA method, model must capture all the images needed to build the internal representation. Updating of the existing eigenspace is only possible when all the images must be kept in order to update the eigenspace, requiring a lot of storage capability. Proposed method allows discarding the acquired images immediately after the update. By experimental results we can show that empirical kernel map has similar accuracy compare to traditional batch way eigenspace method and more efficient in memory requirement than traditional one. This experimental result shows that proposed model is suitable for commercial real time image recognition system.

• Journal of the Korean Data and Information Science Society
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• v.26 no.6
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• pp.1537-1545
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• 2015

Support vector quantile regression (SVQR) can be obtained by applying support vector machine with a check function instead of an e-insensitive loss function into the quantile regression, which still requires to solve a quadratic program (QP) problem which is time and memory expensive. In this paper we propose an SVQR whose objective function is composed of an asymmetric quadratic loss function. The proposed method overcomes the weak point of the SVQR with the check function. We use the iterative procedure to solve the objective problem. Furthermore, we introduce the generalized cross validation function to select the hyper-parameters which affect the performance of SVQR. Experimental results are then presented, which illustrate the performance of proposed SVQR.

• ETRI Journal
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• v.33 no.4
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• pp.652-655
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• 2011

In this letter, we propose a new compression method for a high dimensional support vector machine (SVM). We used singular value decomposition (SVD) to compress the norm part of a radial basis function SVM. By deleting the least significant vectors that are extracted from the decomposition, we can compress each vector with minimized energy loss. We select the compressed vector dimension according to the predefined threshold which can limit the energy loss to design criteria. We verified the proposed vector compressed SVM (VCSVM) for conventional datasets. Experimental results show that VCSVM can reduce computational complexity and memory by more than 40% without reduction in accuracy when classifying a 20,958 dimension dataset.

• Journal of Korea Multimedia Society
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• v.15 no.2
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• pp.266-272
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• 2012

Multilingual support of software is necessary for entering global market. 3-tier architecture is a solution for problems of 2-tier architecture. It divides an application into a client-tier and an application-tier, and presentation logic and database are connected by middleware. The advantage of 3-tier architecture is the enhanced performance through load balancing, scalability, easier maintenance and reusability. This paper proposes a multilingual support method that utilizes common resource files for 3-tier enterprise softwares, applies the proposed method to development of multilingual version of billing solution, and verify the usefulness of it. It is easy for development and maintenance of software, the addition of language supported. Proposed method holds a resource file for each language and provides a multilingual support class library. Therefore this method reduces a waste of memory and disk space. Deployment of a class library into an application tier makes development and maintenance of software, the addition of new language supported easy. To avoid inappropriate modification of a resource file, a multilingual support class library is provided in a dll file.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.120-120
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• 2011

Graphene is a carbon based material and it has great potential of being utilized in various fields such as electronics, optics, and mechanics. In order to develop graphene-based logic systems, graphene field-effect transistor (GFET) has been extensively explored. GFET requires supporting devices, such as volatile memory, to function in an embedded logic system. As far as we understand, graphene has not been studied for volatile memory application, although several graphene non-volatile memories (GNVMs) have been reported. However, we think that these GNVM are unable to serve the logic system properly due to the very slow program/read speed. In this study, a GVM based on the GFET structure and using an engineered graphene channel is proposed. By manipulating the deposition condition, charge traps are introduced to graphene channel, which store charges temporarily, so as to enable volatile data storage for GFET. The proposed GVM shows satisfying performance in fast program/erase (P/E) and read speed. Moreover, this GVM has good compatibility with GFET in device fabrication process. This GVM can be designed to be dynamic random access memory (DRAM) in serving the logic systems application. We demonstrated GVM with the structure of FET. By manipulating the graphene synthesis process, we could engineer the charge trap density of graphene layer. In the range that our measurement system can support, we achieved a high performance of GVM in refresh (>10 ${\mu}s$) and retention time (~100 s). Because of high speed, when compared with other graphene based memory devices, GVM proposed in this study can be a strong contender for future electrical system applications.

• Molecules and Cells
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• v.39 no.6
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• pp.468-476
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• 2016

PLZF-expressing invariant natural killer T cells and CD4 T cells are unique subsets of innate T cells. Both are selected via thymocyte-thymocyte interaction, and they contribute to the generation of activated/memory-like CD4 and CD8 T cells in the thymus via the production of IL-4. Here, we investigated whether $PLZF^+$ innate T cells also affect the development and function of $Foxp3^+$ regulatory CD4 T cells. Flow cytometry analysis of the thymus and spleen from both CIITA transgenic C57BL/6 and wild-type BALB/c mice, which have abundant $PLZF^+$ CD4 T cells and invariant natural killer T cells, respectively, revealed that $Foxp3^+$ T cells in these mice exhibited a $CD103^+$ activated/memorylike phenotype. The frequency of $CD103^+$ regulatory T cells was considerably decreased in $PLZF^+$ cell-deficient $CIITA^{Tg}Plzf^{lu/lu}$ and $BALB/c.CD1d^{-/-}$ mice as well as in an IL-4-deficient background, such as in $CIITA^{Tg}IL-4^{-/-}$ and $BALB/c.IL-4^{-/-}$ mice, indicating that the acquisition of an activated/ memory-like phenotype was dependent on $PLZF^+$ innate T cells and IL-4. Using fetal thymic organ culture, we further demonstrated that IL-4 in concert with TGF-${\beta}$ enhanced the acquisition of the activated/memory-like phenotype of regulatory T cells. In functional aspects, the activated/ memory-like phenotype of Treg cells was directly related to their suppressive function; regulatory T cells of $CIITA^{Tg}PIV^{-/-}$ mice more efficiently suppressed ovalbumin-induced allergic airway inflammation compared with their counterparts from wild-type mice. All of these findings suggest that $PLZF^+$ innate T cells also augmented the generation of activated/memory-like regulation via IL-4 production.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.281-284
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• 2008

Recently, Khronos institude OpenGL ES 2.0 API for support Shader 3.0 model that can possible variable graphic processing. For this reason, the mobile device have need of supporting processor for a shader 3.0 model. We should extend instruction's length to support OpenGL ES 2.0 API, so we need more memory size. In this paper, we propose a new instruction form that adopted variable length and unit instruction architecture. This proposed instruction architecture that support to Shader 3.0 model has consist of 32bit unit instructions up to 4 which can be combined for embellishing each other. Therefore, it can execute flexible instruction combination and reduce waste of instruction fields.

• Journal of the Korean Data and Information Science Society
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• v.24 no.5
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• pp.989-998
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• 2013

We cannot analyze big data, which attracts recent attentions in industry and academy, by batch processing algorithms developed in data mining because big data, by definition, cannot be uploaded and processed in the memory of a single system. So an imminent issue is to develop various leaning algorithms so that they can be applied to big data. In this paper, we review various algorithms for support vector machines in the literature. Particularly, we introduce online type and parallel processing algorithms that are expected to be useful in big data classifications and compare the strengths, the weaknesses and the performances of those algorithms through simulations for linear classification.