• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.266-269
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• 2012

High-efficiency built-in redundancy analysis (BIRA) is presented. The proposed BIRA uses three techniques to achieve a high repair rate using spare mapping registers with adjustable fault tags to reduce area overhead. Simulation results show that the proposed BIRA is a reasonable solution for embedded memories.

• ETRI Journal
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• v.31 no.3
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• pp.339-341
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• 2009

Built-in redundancy analysis (BIRA) is widely used to enhance the yield of embedded memories. In this letter, a new BIRA method for both high repair efficiency and small hardware overhead is presented. The proposed method performs redundancy analysis operations using the spare mapping registers with a covered fault list. Experimental results demonstrate the superiority of the proposed method compared to previous works.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.73-79
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• 2009

With the advance of VLSI technology, the capacity and density of memories are rapidly growing. In this paper we proposed MRI (Memory built-in self Repair Imagination zone) as reallocation algorithm. All faulty cells of embedded memory are reallocated into the row and column spare memory. This work implements reallocation algorithm and BISR to verify its design.

• Proceedings of the Korean Society of Computer Information Conference
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• 2019.01a
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• pp.387-388
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• 2019

As malicious apps vary significantly across Android malware, it is challenging to prevent that the end-users download apps from unsecured app markets. In this paper, we propose an approach to classify the malicious methods based on permissions using Long Short Term Memory (LSTM) that is used to embed the semantics among Intent and permissions. Then the malicious method that is an unsecured method will be removed and re-uploaded to official market. This approach may induce that the end-users download apps from official market in order to reduce the risk of attacks.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.122-130
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• 2013

The demand and the supply are increasing sharply in accordance with the growth of the Memory Semiconductor Industry. The Flash Memory above all is being utilized substantially in the Industry of smart phone, the tablet PC and the System on Chip (SoC). The Flash Memory is divided into the NOR-type Flash Memory and the NAND-type Flash Memory. A lot of study such as the Built-In Self Test (BIST), the Built-In Self Repair (BISR) and the Built-In Redundancy Analysis (BIRA), etc. has been progressed in the NOR-type fash Memory, the study for the Built-In Self Test of the NAND-type Flash Memory has not been progressed. At present, the pattern test of the NAND-type Flash Memory is being carried out using the outside test equipment of high price. The NAND-type Flash Memory is being depended on the outside equipment as there is no Built-In Self Test since the erasure of block unit, the reading and writing of page unit are possible in the NAND-type Flash Memory. The Built-In Self Test equipped with 2 kinds of finite state machine based structure is proposed, so as to carry out the pattern test without the outside pattern test equipment from the NAND-type Flash Memory which carried out the test dependant on the outside pattern test equipment of high price.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1877-1886
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• 2010

In this paper, we design a redundancy control circuit for 1T-SRAM repair using electrical fuse programming. We propose a dual port eFuse cell to provide high program power to the eFuse and to reduce the read current of the cell by using an external program supply voltage when the supply power is low. The proposed dual port eFuse cell is designed to store its programmed datum into a D-latch automatically in the power-on read mode. The layout area of an address comparison circuit which compares a memory repair address with a memory access address is reduced approximately 19% by using dynamic pseudo NMOS logic instead of CMOS logic. Also, the layout size of the designed redundancy control circuit for 1T-SRAM repair using electrical fuse programming with Dongbu HiTek's $0.11{\mu}m$ mixed signal process is $249.02 {\times}225.04{\mu}m^{2}$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.113-120
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• 2007

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. In this paper we proposed reallocation algorithm. All faulty cell of embedded memory is reallocated into the row and column spare memory. This work implements reallocation algorithm and BISR to verify its design.

• Smart Structures and Systems
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• v.4 no.3
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• pp.367-389
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• 2008

Shape Memory Alloys (SMAs) are unique materials with a paramount potential for various applications in bridges. The novelty of this material lies in its ability to undergo large deformations and return to its undeformed shape through stress removal (superelasticity) or heating (shape memory effect). In particular, Ni-Ti alloys have distinct thermomechanical properties including superelasticity, shape memory effect, and hysteretic damping. SMA along with sensing devices can be effectively used to construct smart Reinforced Concrete (RC) bridges that can detect and repair damage, and adapt to changes in the loading conditions. SMA can also be used to retrofit existing deficient bridges. This includes the use of external post-tensioning, dampers, isolators and/or restrainers. This paper critically examines the fundamental characteristics of SMA and available sensing devices emphasizing the factors that control their properties. Existing SMA models are discussed and the application of one of the models to analyze a bridge pier is presented. SMA applications in the construction of smart bridge structures are discussed. Future trends and methods to achieve smart bridges are also proposed.

• The Journal of Information Systems
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• v.31 no.3
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• pp.197-220
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• 2022

Purpose The purpose of this study is to identifies the demand pattern categorization of repair parts of Automotive After-sales Service(A/S) and proposes a demand prediction model for Auto repair parts using Long Short-Term Memory (LSTM) of artificial neural networks (ANN). The optimal parts inventory quantity prediction model is implemented by applying daily, weekly, and monthly the parts demand data to the LSTM model for the Lumpy demand which is irregularly in a specific period among repair parts of the Automotive A/S service. Design/methodology/approach This study classified the four demand pattern categorization with 2 years demand time-series data of repair parts according to the Average demand interval(ADI) and coefficient of variation (CV²) of demand size. Of the 16,295 parts in the A/S service shop studied, 96.5% had a Lumpy demand pattern that large quantities occurred at a specific period. lumpy demand pattern's repair parts in the last three years is predicted by applying them to the LSTM for daily, weekly, and monthly time-series data. as the model prediction performance evaluation index, MAPE, RMSE, and RMSLE that can measure the error between the predicted value and the actual value were used. Findings As a result of this study, Daily time-series data were excellently predicted as indicators with the lowest MAPE, RMSE, and RMSLE values, followed by Weekly and Monthly time-series data. This is due to the decrease in training data for Weekly and Monthly. even if the demand period is extended to get the training data, the prediction performance is still low due to the discontinuation of current vehicle models and the use of alternative parts that they are contributed to no more demand. Therefore, sufficient training data is important, but the selection of the prediction demand period is also a critical factor.

• Journal of the Korea Society of Computer and Information
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• v.26 no.9
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• pp.1-12
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• 2021

In this paper, we propose a tool called ARCAV (Atomatic Recovery of CUDA Atomicity violation) to automatically repair atomicity violations in GPU (Graphics Processing Unit) program. ARCAV monitors information of every barrier and memory to make actual memory writes occur at the end of the barrier region or to make the program execute barrier region again. Existing methods do not repair atomicity violations but only detect the atomicity violations in GPU programs because GPU programs generally do not support lock and sleep instructions which are necessary for repairing the atomicity violations. Proposed ARCAV is designed for GPU execution model. ARCAV detects and repairs four patterns of atomicity violations which represent real-world cases. Moreover, ARCAV is independent of memory hierarchy and thread configuration. Our experiments show that the performance of ARCAV is stable regardless of the number of threads or blocks. The overhead of ARCAV is evaluated using four real-world kernels, and its slowdown is 2.1x, in average, of native execution time.