• 제목/요약/키워드: Memory reduction

검색결과 469건 처리시간 0.026초

정상 노인과 경도인지장애의 감별을 위한 언어 기억과 시공간 기억 검사의 예측 성능 비교 (Comparison of Predictive Performance between Verbal and Visuospatial Memory for Differentiating Normal Elderly from Mild Cognitive Impairment)

  • 변해원
    • 한국융합학회논문지
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    • 제11권6호
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    • pp.203-208
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    • 2020
  • 이 연구는 첫째, 경도인지장애(MCI)가 언어 기억 및 시공간 기억 등 특정 기억의 저하와 관련이 있는지를 파악하고, 둘째, 정상 노인으로부터 MCI를 감별하는 데 예측력이 우수한 지표를 탐색하였다. 표준화 된 기억검사를 수행한 189명(정상 노인 103 명, MCI 86 명)을 분석하였다. 언어 기억은 Seoul Verbal Learning Test를 이용하였고. 시공간 기억은 Rey Complex Figure Test를 이용해서 측정하였다. 다항 로지스틱 회귀모형을 이용하여 기억 검사의 예측력을 분석한 결과, 언어 기억과 시공간 기억은 정상 노인으로부터 MCI를 감별하는 데 예측 성능이 유의미하였다. 반면, 각 기억 검사의 수행결과를 포함하여 모든 혼란변수를 보정했을 때, 언어 기억의 즉시 회상만 정상 노인으로부터 MCI를 감별하는 데 예측력이 유의미하였으며, 시공간 기억의 즉시 회상은 예측력이 유의미하지 않았다. 이 결과는 MCI를 선별할 때 언어 기억과 시공간 기억의 지연 회상, 언어 기억의 즉시 회상이 MCI의 기억능력을 감별할 수 있는 최상의 조합임을 시사한다.

JPEG2000 시스템의 코드블록 메모리 크기 및 대역폭 감소를 위한 Multi-mode Embedded Compression 알고리즘 및 구조 (Multi-mode Embedded Compression Algorithm and Architecture for Code-block Memory Size and Bandwidth Reduction in JPEG2000 System)

  • 손창훈;박성모;김영민
    • 대한전자공학회논문지SD
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    • 제46권8호
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    • pp.41-52
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    • 2009
  • Motion JPEG2000과 같은 동영상 압축 시스템에서는 데이터 메모리에 대한 빈번한 접근이 전체 시스템에 큰 병목 현상이 된다. 이처럼 시스템에서 요구하는 메모리의 대역폭을 감소시키기 위해서, 본 논문은 약간의 화질 손실이 있는 새로운 embedded compression(EC) 알고리즘과 구조를 고안하였다. 또한, 메모리 내의 압축된 데이터에 임의 접근성(Random Accessibility)과 짧은 지연 시간(Latency)을 보장하기 위해서 매우 단순하면서도 효율적인 entropy 부호화 방법을 제안하였다. 본 논문에서는 JPEG2000 표준안 알고리즘에는 어떠한 변경도 하지 않으면서, 제안한 multi-mode 알고리즘을 통해 JPEG2000 시스템에서 요구하는 메모리의 대역폭의 감소(약 52${\sim}$81%) 와 코드블록 메모리의 크기를 약 2 배 이상 감소시킬 수 있었다.

Multi-operation-based Constrained Random Verification for On-Chip Memory

  • Son, Hyeonuk;Jang, Jaewon;Kim, Heetae;Kang, Sungho
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제15권3호
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    • pp.423-426
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    • 2015
  • Current verification methods for on-chip memory have been implemented using coverpoints that are generated based on a single operation. These coverpoints cannot consider the influence of other memory banks in a busy state. In this paper, we propose a method in which the coverpoints account for all operations executed on different memory banks. In addition, a new constrained random vector generation method is proposed to reduce the required random vectors for the multi-operation-based coverpoints. The simulation results on NAND flash memory show 100% coverage with 496,541 constrained random vectors indicating a reduction of 96.4% compared with conventional random vectors.

실시간 시스템에서의 플래시 메모리 저장 장치를 위한 적응적 가비지 컬렉션 정책 (A Adaptive Garbage Collection Policy for Flash-Memory Storage System in Embedded Systems)

  • 박송화;이정훈;이원오;김희언
    • 대한임베디드공학회논문지
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    • 제12권3호
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    • pp.121-130
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    • 2017
  • NAND flash memory has advantages of non-volatility, little power consumption and fast access time. However, it suffers from inability that does not provide to update-in-place and the erase cycle is limited. Moreover, the unit of read/write operation is a page and the unit of erase operation is a block. Therefore, erase operation is slower than other operations. The AGC, the proposed garbage collection policy focuses on not only garbage collection time reduction for real-time guarantee but also wear-leveling for a flash memory lifetime. In order to achieve above goals, we define three garbage collection operating modes: Fast Mode, Smart Mode, and Wear-leveling Mode. The proposed policy decides the garbage collection mode depending on system CPU usage rate. Fast Mode selects the dirtiest block as victim block to minimize the erase operation time. However, Smart Mode selects the victim block by reflecting the invalid page number and block erase count to minimizing the erase operation time and deviation of block erase count. Wear-leveling Mode operates similar to Smart Mode and it makes groups and relocates the pages which has the similar update time. We implemented the proposed policy and measured the performance compare with the existing policies. Simulation results show that the proposed policy performs better than Cost-benefit policy with the 55% reduction in the operation time. Also, it performs better than Greedy policy with the 87% reduction in the deviation of erase count. Most of all, the proposed policy works adaptively according to the CPU usage rate, and guarantees the real-time performance of the system.

MLC NAND 플래시 메모리의 셀 간 간섭현상 감소를 위한 등화기 알고리즘 (An Equalizing Algorithm for Cell-to-Cell Interference Reduction in MLC NAND Flash Memory)

  • 김두환;이상진;남기훈;김시호;조경록
    • 전기학회논문지
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    • 제59권6호
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    • pp.1095-1102
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    • 2010
  • This paper presents an equalizer reducing CCI(cell-to-cell interference) in MLC NAND flash memory. High growth of the flash memory market has been driven by two combined technological efforts that are an aggressive scaling technique which doubles the memory density every year and the introduction of MLC(multi level cell) technology. Therefore, the CCI is a critical factor which affects occurring data errors in cells. We introduced an equation of CCI model and designed an equalizer reducing CCI based on the proposed equation. In the model, we have been considered the floating gate capacitance coupling effect, the direct field effect, and programming methods of the MLC NAND flash memory. Also we design and verify the proposed equalizer using Matlab. As the simulation result, the error correction ratio of the equalizer shows about 20% under 20nm NAND process where the memory channel model has serious CCI.

Efficient Management of PCM-based Swap Systems with a Small Page Size

  • Park, Yunjoo;Bahn, Hyokyung
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제15권5호
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    • pp.476-484
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    • 2015
  • Due to the recent advances in non-volatile memory technologies such as PCM, a new memory hierarchy of computer systems is expected to appear. In this paper, we explore the performance of PCM-based swap systems and discuss how this system can be managed efficiently. Specifically, we introduce three management techniques. First, we show that the page fault handling time can be reduced by attaching PCM on DIMM slots, thereby eliminating the software stack overhead of block I/O and the context switch time. Second, we show that it is effective to reduce the page size and turn off the read-ahead option under the PCM swap system where the page fault handling time is sufficiently small. Third, we show that the performance is not degraded even with a small DRAM memory under a PCM swap device; this leads to the reduction of DRAM's energy consumption significantly compared to HDD-based swap systems. We expect that the result of this paper will lead to the transition of the legacy swap system structure of "large memory - slow swap" to a new paradigm of "small memory - fast swap."

Design and Performance Analysis of Pre-Distorter Including HPA Memory Effect

  • An, Dong-Geon;Lee, Il-Jin;Ryu, Heung-Gyoon
    • Journal of electromagnetic engineering and science
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    • 제9권2호
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    • pp.71-77
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    • 2009
  • OFDM(Orthogonal Frequency Division Multiplexing) signals sutler serious nonlinear distortion in the nonlinear HPA(High Power Amplifier) because of high PAPR(Peak Average Power Ratio). Nonlinear distortion can be improved by a pre-distorter, but this pre-distorter is insufficient when the PAPR is very high in an OPFDM system. In this paper, a DFT(Discrete Fourier Transform) transform technique is introduced for PAPR reduction. It is especially important to consider the memory effect of HPA for more precise predistortion. Therefore, in this paper, we consider two models, the TWTA(Traveling-Wave Tube Amplifier) model of Saleh without a memory effect and the HPA memory polynomial model that has a memory effect. We design a pre-distorter and an adaptive pre-distorter that uses the NLMS(Normalized Least Mean Square) algorithm for the compensation of this nonlinear distortion. Without the consideration of a memory effect, the system performance would be degraded, even if the pre-distorter is used for the compensation of the nonlinear distortion. From the simulation results, we can confirm that the proposed system shows an improvement in performance.

Pt 나노입자와 Hybrid Pt-$SiO_2$ 나노입자의 합성과 활용 및 입자박막 제어 (Synthesis and application of Pt and hybrid Pt-$SiO_2$ nanoparticles and control of particles layer thickness)

  • 최병상
    • 한국전자통신학회논문지
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    • 제4권4호
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    • pp.301-305
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    • 2009
  • Pt 나노입자의 합성과 이를 이용한 hybrid Pt-$SiO_2$ 나노입자의 합성을 성공적으로 수행하였으며, self-assembled Pt nanoparticles monolayer를 charge trapping layer로 활용하는 metal-oxide-semiconductor(MOS) type memory의 한 예로 non-volatile memory(NVM)의 응용을 보임으로써 나노입자의 활용 가능성을 보이고, 또한, hybrid Pt-$SiO_2$ 나노입자 박막 층의 제어를 통한 MOS type memory device에의 보다 더 넓은 활용 가능성을 보이고자 하였다.

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Effects of fermented ginseng on memory impairment and β-amyloid reduction in Alzheimer's disease experimental models

  • Kim, Joonki;Kim, Sung Hun;Lee, Deuk-Sik;Lee, Dong-Jin;Kim, Soo-Hyun;Chung, Sungkwon;Yang, Hyun Ok
    • Journal of Ginseng Research
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    • 제37권1호
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    • pp.100-107
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    • 2013
  • This study examined the effect of fermented ginseng (FG) on memory impairment and ${\beta}$-amyloid ($A{\beta}$) reduction in models of Alzheimer's disease (AD) in vitro and in vivo. FG extract was prepared by steaming and fermenting ginseng. In vitro assessment measured soluble $A{\beta}42$ levels in HeLa cells, which stably express the Swedish mutant form of amyloid precursor protein. After 8 h incubation with the FG extract, the level of soluble $A{\beta}42$ was reduced. For behavioral assessments, the passive avoidance test was used for the scopolamine-injected ICR mouse model, and the Morris water maze was used for a transgenic (TG) mouse model, which exhibits impaired memory function and increased $A{\beta}42$ level in the brain. FG extract was treated for 2 wk or 4 mo on ICR and TG mice, respectively. FG extract treatment resulted in a significant recovery of memory function in both animal models. Brain soluble $A{\beta}42$ levels measured from the cerebral cortex of TG mice were significantly reduced by the FG extract treatment. These findings suggest that FG extract can protect the brain from increased levels of $A{\beta}42$ protein, which results in enhanced behavioral memory function, thus, suggesting that FG extract may be an effective preventive or treatment for AD.

21C Korean Lithography Roadmap

  • Baik, Ki-Ho;Yim, Dong-Gyu;Kim, Young-Sik
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1999년도 하계종합학술대회 논문집
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    • pp.269-274
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    • 1999
  • As the semiconductor industry enters the next century, we are facing to the technological changes and challenges. Optical lithography has driven by the miniaturisation of semiconductor devices and has been accompanied by an increase in wafer productivity and performance through the reduction of the IC image geometries. In the last decade, DRAM(Dynamic Random Access Memories) have been quadrupoling in level of integration every two years. Korean chip makers have been produced the memory devices, mainly DRAM, which are the driving force of IC's(Integrated Circuits) development and are the technology indicator for advanced manufacturing. Therefore, Korean chip makers have an important position to predict and lead the patterning technology. In this paper, we will be discussed the limitations of the optical lithography, such as KrF and ArF. And, post optical lithography technology, such as E-beam lithography, EUV and E-beam Projection Lithography shall be introduced.

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