[KSCI] Korea Science Citation Index Service

http://dx.doi.org/10.5573/JSTS.2015.15.3.423

Multi-operation-based Constrained Random Verification for On-Chip Memory

Son, Hyeonuk (Department of Electrical and Electronic Engineering, Yonsei University)
Jang, Jaewon (Department of Electrical and Electronic Engineering, Yonsei University)
Kim, Heetae (Department of Electrical and Electronic Engineering, Yonsei University)
Kang, Sungho (Department of Electrical and Electronic Engineering, Yonsei University)

Publication Information

JSTS:Journal of Semiconductor Technology and Science / v.15, no.3, 2015 , pp. 423-426 More about this Journal

Abstract

Current verification methods for on-chip memory have been implemented using coverpoints that are generated based on a single operation. These coverpoints cannot consider the influence of other memory banks in a busy state. In this paper, we propose a method in which the coverpoints account for all operations executed on different memory banks. In addition, a new constrained random vector generation method is proposed to reduce the required random vectors for the multi-operation-based coverpoints. The simulation results on NAND flash memory show 100% coverage with 496,541 constrained random vectors indicating a reduction of 96.4% compared with conventional random vectors.

Keywords

Constrained random verification (CRV); functional verification; coverpoint; NAND flash; constrained random vector;

Citations & Related Records

Reference

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