• Journal of the Korea Convergence Society
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• v.11 no.6
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• pp.203-208
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• 2020

This study examined whether Mild Cognitive Impairment (MCI) is related to the reduction of specific memory among linguistic memory and visuospatial memory, and to identify the most predictive index for discriminating MCI from normal elderly. The subjects were analyzed for 189 elderly (103 healthy elderly, 86 MCI). The verbal memory was used by the Seoul Verbal Learning Test. visuospatial memory was measured using the Rey Complex Figure Test. As a result of multiple logistic regression, verbal memory and visuospatial memory showed significant predictive performance in discriminating MCI from normal elderly. On the other hand, when all the confounding variables were corrected, including the results of each memory test, the predictive power was significant in distinguishing MCI from normal aging only in the immediate recall of verbal memory, and the predictive power was not significant in the immediate recall of visuospatial memory. This result suggests that delayed recall of visuospatial memory and immediate recall of verbal memory are the best combinations to discriminate memory ability of MCI.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.41-52
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• 2009

In Motion JPEG2000 encoding, huge bandwidth requirement of data memory access is the bottleneck in required system performance. For the alleviation of this bandwidth requirement, a new embedded compression(EC) algorithm with a little bit of image quality drop is devised. For both random accessibility and low latency, very simple and efficient entropy coding algorithm is proposed. We achieved significant memory bandwidth reductions (about 53${\sim}$81%) and reduced code-block memory to about half size through proposed multi-mode algorithms, without requiring any modification in JPEG2000 standard algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.423-426
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• 2015

Current verification methods for on-chip memory have been implemented using coverpoints that are generated based on a single operation. These coverpoints cannot consider the influence of other memory banks in a busy state. In this paper, we propose a method in which the coverpoints account for all operations executed on different memory banks. In addition, a new constrained random vector generation method is proposed to reduce the required random vectors for the multi-operation-based coverpoints. The simulation results on NAND flash memory show 100% coverage with 496,541 constrained random vectors indicating a reduction of 96.4% compared with conventional random vectors.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.3
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• pp.121-130
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• 2017

NAND flash memory has advantages of non-volatility, little power consumption and fast access time. However, it suffers from inability that does not provide to update-in-place and the erase cycle is limited. Moreover, the unit of read/write operation is a page and the unit of erase operation is a block. Therefore, erase operation is slower than other operations. The AGC, the proposed garbage collection policy focuses on not only garbage collection time reduction for real-time guarantee but also wear-leveling for a flash memory lifetime. In order to achieve above goals, we define three garbage collection operating modes: Fast Mode, Smart Mode, and Wear-leveling Mode. The proposed policy decides the garbage collection mode depending on system CPU usage rate. Fast Mode selects the dirtiest block as victim block to minimize the erase operation time. However, Smart Mode selects the victim block by reflecting the invalid page number and block erase count to minimizing the erase operation time and deviation of block erase count. Wear-leveling Mode operates similar to Smart Mode and it makes groups and relocates the pages which has the similar update time. We implemented the proposed policy and measured the performance compare with the existing policies. Simulation results show that the proposed policy performs better than Cost-benefit policy with the 55% reduction in the operation time. Also, it performs better than Greedy policy with the 87% reduction in the deviation of erase count. Most of all, the proposed policy works adaptively according to the CPU usage rate, and guarantees the real-time performance of the system.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.6
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• pp.1095-1102
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• 2010

This paper presents an equalizer reducing CCI(cell-to-cell interference) in MLC NAND flash memory. High growth of the flash memory market has been driven by two combined technological efforts that are an aggressive scaling technique which doubles the memory density every year and the introduction of MLC(multi level cell) technology. Therefore, the CCI is a critical factor which affects occurring data errors in cells. We introduced an equation of CCI model and designed an equalizer reducing CCI based on the proposed equation. In the model, we have been considered the floating gate capacitance coupling effect, the direct field effect, and programming methods of the MLC NAND flash memory. Also we design and verify the proposed equalizer using Matlab. As the simulation result, the error correction ratio of the equalizer shows about 20% under 20nm NAND process where the memory channel model has serious CCI.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.476-484
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• 2015

Due to the recent advances in non-volatile memory technologies such as PCM, a new memory hierarchy of computer systems is expected to appear. In this paper, we explore the performance of PCM-based swap systems and discuss how this system can be managed efficiently. Specifically, we introduce three management techniques. First, we show that the page fault handling time can be reduced by attaching PCM on DIMM slots, thereby eliminating the software stack overhead of block I/O and the context switch time. Second, we show that it is effective to reduce the page size and turn off the read-ahead option under the PCM swap system where the page fault handling time is sufficiently small. Third, we show that the performance is not degraded even with a small DRAM memory under a PCM swap device; this leads to the reduction of DRAM's energy consumption significantly compared to HDD-based swap systems. We expect that the result of this paper will lead to the transition of the legacy swap system structure of "large memory - slow swap" to a new paradigm of "small memory - fast swap."

• Journal of electromagnetic engineering and science
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• v.9 no.2
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• pp.71-77
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• 2009

OFDM(Orthogonal Frequency Division Multiplexing) signals sutler serious nonlinear distortion in the nonlinear HPA(High Power Amplifier) because of high PAPR(Peak Average Power Ratio). Nonlinear distortion can be improved by a pre-distorter, but this pre-distorter is insufficient when the PAPR is very high in an OPFDM system. In this paper, a DFT(Discrete Fourier Transform) transform technique is introduced for PAPR reduction. It is especially important to consider the memory effect of HPA for more precise predistortion. Therefore, in this paper, we consider two models, the TWTA(Traveling-Wave Tube Amplifier) model of Saleh without a memory effect and the HPA memory polynomial model that has a memory effect. We design a pre-distorter and an adaptive pre-distorter that uses the NLMS(Normalized Least Mean Square) algorithm for the compensation of this nonlinear distortion. Without the consideration of a memory effect, the system performance would be degraded, even if the pre-distorter is used for the compensation of the nonlinear distortion. From the simulation results, we can confirm that the proposed system shows an improvement in performance.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.4
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• pp.301-305
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• 2009

Pt nanoparticles with a narrow size distribution (dia. ~4 nm) were synthesized via an alcohol reduction method and used for the fabrication of hybrid Pt-$SiO_2$ nanoparticles. Also, the self-assembled monolayer of Pt nanoparticles (NPs) was studied as a charge trapping layer for non-volatile memory (NVM) applications. A metal-oxide-semiconductor (MOS) type memory device with Pt NPs exhibits a relatively large memory window. These results indicate that the self-assembled Pt NPs can be utilized for NVM devices. In addition, it was tried to show the control of thin-film thickness of hybrid Pt-$SiO_2$ nanoparticles indicating the possibility of much applications for the MOS type memory devices.

• Journal of Ginseng Research
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• v.37 no.1
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• pp.100-107
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• 2013

This study examined the effect of fermented ginseng (FG) on memory impairment and ${\beta}$-amyloid ($A{\beta}$) reduction in models of Alzheimer's disease (AD) in vitro and in vivo. FG extract was prepared by steaming and fermenting ginseng. In vitro assessment measured soluble $A{\beta}42$ levels in HeLa cells, which stably express the Swedish mutant form of amyloid precursor protein. After 8 h incubation with the FG extract, the level of soluble $A{\beta}42$ was reduced. For behavioral assessments, the passive avoidance test was used for the scopolamine-injected ICR mouse model, and the Morris water maze was used for a transgenic (TG) mouse model, which exhibits impaired memory function and increased $A{\beta}42$ level in the brain. FG extract was treated for 2 wk or 4 mo on ICR and TG mice, respectively. FG extract treatment resulted in a significant recovery of memory function in both animal models. Brain soluble $A{\beta}42$ levels measured from the cerebral cortex of TG mice were significantly reduced by the FG extract treatment. These findings suggest that FG extract can protect the brain from increased levels of $A{\beta}42$ protein, which results in enhanced behavioral memory function, thus, suggesting that FG extract may be an effective preventive or treatment for AD.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.269-274
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• 1999

As the semiconductor industry enters the next century, we are facing to the technological changes and challenges. Optical lithography has driven by the miniaturisation of semiconductor devices and has been accompanied by an increase in wafer productivity and performance through the reduction of the IC image geometries. In the last decade, DRAM(Dynamic Random Access Memories) have been quadrupoling in level of integration every two years. Korean chip makers have been produced the memory devices, mainly DRAM, which are the driving force of IC＇s(Integrated Circuits) development and are the technology indicator for advanced manufacturing. Therefore, Korean chip makers have an important position to predict and lead the patterning technology. In this paper, we will be discussed the limitations of the optical lithography, such as KrF and ArF. And, post optical lithography technology, such as E-beam lithography, EUV and E-beam Projection Lithography shall be introduced.