• 대한전기학회논문지:시스템및제어부문D
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• 제51권8호
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• pp.344-351
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• 2002

The proposed immune algorithm has an uncomplicated structure and memory-cell mechanism as the optimization algorithm which imitates the principle of humoral immune response. We use the proposed algorithm to solve parameter optimization problems. Up to now, the applications of immune algorithm have been optimization problems with non-varying system parameters. Therefore the usefulness of memory-cell mechanism in immune algorithm is without. This paper proposes the immune algorithm using a memory-cell mechanism which can be the application of system with nonlinear varying parameters. To verified performance of the proposed immune algorithm, the speed control of nonlinear DC motor are performed. The results of Computer simulations represent that the proposed immune algorithm shows a fast convergence speed and a good control performances under the varying system parameters.

• 대한수학회지
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• 제47권4호
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• pp.767-788
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• 2010

In this paper, we propose two limited memory BFGS algorithms with a nonmonotone line search technique for unconstrained optimization problems. The global convergence of the given methods will be established under suitable conditions. Numerical results show that the presented algorithms are more competitive than the normal BFGS method.

• ETRI Journal
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• 제42권4호
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• pp.505-517
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• 2020

The increasing size and complexity of deep neural networks (DNNs) necessitate the development of efficient high-performance accelerators. An efficient memory structure and operating scheme provide an intuitive solution for high-performance accelerators along with dataflow control. Furthermore, the processing of various neural networks (NNs) requires a flexible memory architecture, programmable control scheme, and automated optimizations. We first propose an efficient architecture with flexibility while operating at a high frequency despite the large memory and PE-array sizes. We then improve the efficiency and usability of our architecture by automating the optimization algorithm. The experimental results show that the architecture increases the data reuse; a diagonal write path improves the performance by 1.44× on average across a wide range of NNs. The automated optimizations significantly enhance the performance from 3.8× to 14.79× and further provide usability. Therefore, automating the optimization as well as designing an efficient architecture is critical to realizing high-performance DNN accelerators.

• 한국전산구조공학회:학술대회논문집
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• 한국전산구조공학회 2006년도 정기 학술대회 논문집
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• pp.291-298
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• 2006

A parallelized topology design optimization method is developed on a distributed memory system. The parallelization is based on a domain decomposition method and a boundary communication scheme. For the finite element analysis of structural responses and design sensitivities, the PCG method based on a Krylov iterative scheme is employed. Also a parallelized optimization method of optimality criteria is used to solve large-scale topology optimization problems. Through several numerical examples, the developed method shows efficient and acceptable topology optimization results for the large-scale problems.

• 한국인터넷방송통신학회논문지
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• 제21권6호
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• pp.141-145
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• 2021

다양한 형태의 메모리 아키텍처가 개발되었고, 이를 효과적으로 사용하기 위한 여러 컴파일러 최적화 기법이 연구되었다. 특히, 모바일 컴퓨팅 디바이스에서 메모리는 성능을 결정하는 주요 컴포넌트이기 때문에 이를 지원하기 위한 다양한 최적화 기법들이 개발되었다. 최근에는 하이브리드 형태의 메모리 아키텍처에 대한 연구가 많이 진행되고 있기 때문에 이를 지원하기 위한 다양한 컴파일러 기법이 연구되고 있다. 시장의 요구조건에 맞추어 저전력에 대한 제약조건과 필요한 최소한의 성능을 달성하기 위하여 기존의 컴파일러 최적화 기법들이 사용될 수 있다. 이러한 최적화 기법들을 활용한 저전력 효과 및 성능 개선 정도를 파악하기 위한 레퍼런스가 제대로 제공되지 못하고 있는 실정이다. 본 연구는 기존의 컴파일러 기법에 대한 실험 결과를 멀티뱅크 메모리 아키텍처 개발의 레퍼런스로 제공하기 위하여 진행되었다.

• 대한수학회지
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• 제47권1호
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• pp.63-70
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• 2010

In this paper, we develop a nonmonotone spectral memory gradient method for unconstrained optimization, where the spectral stepsize and a class of memory gradient direction are combined efficiently. The global convergence is obtained by using a nonmonotone line search strategy and the numerical tests are also given to show the efficiency of the proposed algorithm.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 2002년도 춘계학술대회 및 임시총회
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• pp.175-178
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• 2002

The proposed immune algorithm has an uncomplicated structure and memory-cell mechanism as the optimization algorithm which imitates the principle of humoral immune response, and has been used as methods to solve parameter optimization problems. Up to now, the applications of immune algorithm have been optimization problems with non-varying system parameters. Therefore, the effect of memory-cell mechanism, which is a merit of immune algorithm, is without. this paper proposes the immune algorithm using a memory-cell mechanism which can be the application of system with nonlinear varying parameters. To verified performance of the proposed immune algorithm, the speed control of nonlinear DC motor are performed. Computer simulation studies show that the proposed immune algorithm has a fast convergence speed and a good control performances under the varying system parameters.

• International journal of advanced smart convergence
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• 제6권1호
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• pp.26-31
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• 2017

When mobile navigator device accesses data randomly, the cache memory performance is rapidly deteriorated due to low memory access locality. For instance, GPS (General Positioning System) of navigator program for automobiles or drones, that are currently in common use, uses data from 32 satellites and computes current position of a receiver. This computation of positioning is the major part of GPS which accounts more than 50% computation in the program. In this computation task, the satellite signals are received in real time and stored in buffer memories. At this task, since necessary data cannot be sequentially stored, the data is read and used at random. This data accessing patterns are generated randomly, thus, memory system performance is worse by low data locality. As a result, it is difficult to process data in real time due to low data localization. Improving the low memory access locality inherited on the algorithms of conventional communication applications requires a certain optimization technique to solve this problem. In this study, we try to do optimizations with data and memory to improve the locality problem. In experiment, we show that our case study can improve processing speed of core computation and improve our overall system performance by 14%.

• 한국정보과학회논문지:시스템및이론
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• 제36권2호
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• pp.102-110
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• 2009

컴퓨터 시스템 분야의 대표적인 문제 중 하나는 메모리의 처리 속도가 CPU의 처리 속도보다 매우 느리기 때문에 생기는 CPU 휴면 시간의 증가, 즉 메모리 장벽 문제이다. CPU와 메모리의 속도 차이를 줄이기 위해서는 레지스터, 캐시 메모리, 메인 메모리, 디스크로 대표되는 메모리 계층을 이용하여 자주 쓰이는 데이터를 메모리 계층 상위, 즉 CPU 가까이 위치시켜야 한다. 본 논문에서는 On-Chip SRAM을 이용한 임베디드 시스템 메모리 계층 최적화 기법을 리눅스 기반 시스템에서 최초로 제안한다. 본 기법은 시스템의 가상 메모리를 이용하여 프로그래머가 원하는 코드나 데이터를 On-Chip SRAM에 적재한다. 제안된 기법의 실험 결과 총 9개의 어플리케이션에 대하여 최대 35%, 평균 14%의 시스템 성능 향상과 최대 40% 평균 15%의 에너지 소비 감소를 보였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.391-406
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• 2014

The performance of General-Purpose computation on Graphics Processing Units (GPGPU) is heavily dependent on the memory access behavior. This sensitivity is due to a combination of the underlying Massively Parallel Processing (MPP) execution model present on GPUs and the lack of architectural support to handle irregular memory access patterns. Application performance can be significantly improved by applying memory-access-pattern-aware optimizations that can exploit knowledge of the characteristics of each access pattern. In this paper, we present an algorithmic methodology to semi-automatically find the best mapping of memory accesses present in serial loop nest to underlying data-parallel architectures based on a comprehensive static memory access pattern analysis. To that end we present a simple, yet powerful, mathematical model that captures all memory access pattern information present in serial data-parallel loop nests. We then show how this model is used in practice to select the most appropriate memory space for data and to search for an appropriate thread mapping and work group size from a large design space. To evaluate the effectiveness of our methodology, we report on execution speedup using selected benchmark kernels that cover a wide range of memory access patterns commonly found in GPGPU workloads. Our experimental results are reported using the industry standard heterogeneous programming language, OpenCL, targeting the NVIDIA GT200 architecture.