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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Automated optimization for memory-efficient high-performance deep neural network accelerators

  • Kim, HyunMi (AI SoC Research Division, Electronics and Telecommunications Research Institute) ;
  • Lyuh, Chun-Gi (AI SoC Research Division, Electronics and Telecommunications Research Institute) ;
  • Kwon, Youngsu (AI SoC Research Division, Electronics and Telecommunications Research Institute)
  • Received : 2020.03.28
  • Accepted : 2020.07.02
  • Published : 2020.08.18
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Abstract

The increasing size and complexity of deep neural networks (DNNs) necessitate the development of efficient high-performance accelerators. An efficient memory structure and operating scheme provide an intuitive solution for high-performance accelerators along with dataflow control. Furthermore, the processing of various neural networks (NNs) requires a flexible memory architecture, programmable control scheme, and automated optimizations. We first propose an efficient architecture with flexibility while operating at a high frequency despite the large memory and PE-array sizes. We then improve the efficiency and usability of our architecture by automating the optimization algorithm. The experimental results show that the architecture increases the data reuse; a diagonal write path improves the performance by 1.44× on average across a wide range of NNs. The automated optimizations significantly enhance the performance from 3.8× to 14.79× and further provide usability. Therefore, automating the optimization as well as designing an efficient architecture is critical to realizing high-performance DNN accelerators.

Keywords

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