• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.52-60
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• 2008

The deblocking filter in the H.264/AVC video coding standard helps to reduce the blocking artifacts produced in the decoding process. But it consumes one third of the computational complexity in H.624/AVC decoder, which advocates an efficient design of a hardware accelerator for filtering. This paper proposes an architecture of deblocking filter using two filters and some registers for data reuse. Our architecture improves the throughput and minimize the number of external memory access by increasing data reuse. After initialization, two filters are able to perform filtering operation simultaneously. It takes only 96 clocks to complete filtering for one macroblock. We design and synthesis our architecture using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 200MHz.

• Journal of IKEEE
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• v.17 no.3
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• pp.324-331
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• 2013

In this paper, we implemented memristor emulator circuit on Printed Circuit Board (PCB) and observed the inherent pinched hysteresis characteristic of memristors by measuring the emulator circuit on PCB. The memristor emulator circuit implemented on PCB is composed of simple discrete devices not using any complicated circuit blocks thus we can integrate the memristor emulator circuits in very small layout area on Silicon substrate. The programmable gain amplifier is designed using the proposed memristor emulator circuit and verified that the amplifier's voltage gain can be controlled by programming memristance of the emulator circuit by circuit simulation. Threshold switching is also realized in the proposed emulator circuit thus memristance can remain unchanged when the input voltage applied to the emulator circuit is lower than VREF. The memristor emulator circuit and the programmable gain amplifier using the proposed circuit can be useful in teaching the device operation, functions, characteristics, and applications of memristors to students when thet cannot access to device and fabrication technologies of real memristors.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.5
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• pp.12-19
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• 2007

This paper presents an ASIP(Application Specific Instruction Set Processor) for implementation of H.264/AVC, called VSIP(Video Specific Instruction-set Processor). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has hardware accelerators for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. The proposed VSIP can efficiently perform in real-time video processing and it can support various profiles and standards.

• Journal of the Korean Magnetics Society
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• v.25 no.2
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• pp.47-51
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• 2015

To achieve a high tunneling magneto resistance (TMR) of sputtered magnetic tunnel junctions (MTJs) with an MgO barrier, the annealing process is indispensable. The structural and compositional changes as consequences of the annealing greatly affect the spin-dependent transport properties of MTJs. Higher TMR could be obtained for MTJs annealed at higher annealing temperature. The diffusion of Ru, Mn and/or Ta in the MTJs may occur during annealing process, which is known to be detrimental to spin-dependent tunneling effect. The rapid thermal annealing (RTA) process was used for annealing the MTJs with synthetic antiferromagnets. To suppress the diffusion of Mn, Ru and/or Ta in the MTJs, the process time and temperature of RTA were minutely controlled.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.1-6
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• 2000

Recently, SrBi$_{2}$Ta$_{2}$ $O_{9}$(SBT) and Pb(Zr,Ti) $O_{3}$(PZT) were much attracted as materials of capacitor for ferroelectric random access memory(FRAM) with higher read/ write speed, lower power consumption and nonvolartility. SBT thin film has appeared as the most prominent fatigue free and low operation voltage. To highly integrate FRAM, SBT thin film has to be etched. A lot of papers have been reported over growth of SBT thin film and its characteristics. However, there are few reports about etching SBT thin film owing to difficult of etching ferroelectric materials. SBT thin film was etched in CF$_{4}$Ar plasma using magnetically enhanced inductively coupled plasma (MEICP) system. In order to investigate the chemical reaction on the etched surface of SBT thin films, X-ray Photoelecton spectrosocpy (XPS) and Secondary ion mass spectroscopy(SIMS) was performed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.5
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• pp.268-273
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• 2016

In this study, we observed current-voltage characteristics of the MIM (metal-insulator-metal) structure. The $WO_x$ material was used between metal electrodes as the oxide insulator. The structure of the $Al/WO_x/TiN$ shows bipolar resistive switching and the operating direction of the resistive switching is clockwise, which means set at negative voltage and reset at positive voltage. The set process from HRS (high resistance state) to LRS (low resistance state) occurred at -2.6V. The reset process from LRS to HRS occurred at 2.78V. The on/off current ratio was about 10 and resistive switching was performed for 5 cycles in the endurance characteristics. With consecutive switching cycles, the stable $V_{set}$ and $V_{reset}$ were observed. The electrical transport mechanism of the device was based on the migration of oxygen ions and the current-voltage curve is following (Ohm's Law ${\rightarrow}$ Trap-Controlled Space Charge Limited Current ${\rightarrow}$ Ohm's Law) process in the positive voltage region.

• Journal of Computing Science and Engineering
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• v.12 no.1
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• pp.24-35
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• 2018

Deep convolutional neural network (DCNN) is an advanced technology in image recognition. Because of extreme computing resource requirements, DCNN implementation with software alone cannot achieve real-time requirement. Therefore, the need to implement DCNN accelerator hardware is increasing. In this paper, we present a field programmable gate array (FPGA)-based hardware accelerator design of DCNN targeting handwritten Hangul character recognition application. Also, we present design optimization techniques in SDAccel environments for searching the optimal FPGA design space. The techniques we used include memory access optimization and computing unit parallelism, and data conversion. We achieved about 11.19 ms recognition time per character with Xilinx FPGA accelerator. Our design optimization was performed with Xilinx HLS and SDAccel environment targeting Kintex XCKU115 FPGA from Xilinx. Our design outperforms CPU in terms of energy efficiency (the number of samples per unit energy) by 5.88 times, and GPGPU in terms of energy efficiency by 5 times. We expect the research results will be an alternative to GPGPU solution for real-time applications, especially in data centers or server farms where energy consumption is a critical problem.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1031-1038
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• 2005

In this paper, we propose real-time 3D image converting architecture by a unit of pixel for 2D/3D compatible PC and LCD of cellular phone with parallax burier, and implement a system for overall display operation after designing a circuit based on FPGA. After digitizing anolog image signal from PC, we recompose it to 3D image signal according to input image type. Since the architecture which rearranges 2D image to 3D depends on parallax burier, we use interleaving method which mixes pixels by a unit of R, G, and B cell. The propose architecture is designed into a circuit based on FPGA with high-speed memory access technique and use 4 SDRAMs for high performance data storing and processing. The implemented system consists of A/D converting system, FPGA system to formatting 2D signal to 3D, and LCD panel with parallax barrier, for 3D display.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.306.1-306.1
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• 2014

정보화 시대의 발전에 따라 점점 더 많은 정보를 더욱 빠르게 처리할 수 있는 기기들이 요구되고 있다. 메모리는 그 중에서 핵심적인 부품으로써 소자의 고집적화와 고속화가 계속 진행되면서 기존의 메모리 소자들은 집적화에서 그 한계에 도달하고 있다. 기존 소자들의 집적화의 한계를 극복하기 위하여 새로운 비휘발성 메모리 소자들이 제안되었다. 그 중 resistive switching random access memory(ReRAM)은 저항의 변화특성을 사용하는 메모리로 간단한 구조를 가지고 있기 때문에 집적화에 유리하다는 장점을 가지고 있다. 그 외에도 빠른 동작 속도와 낮은 전압에서의 동작이 가능하여 차세대 메모리로써 각광받고 있는 추세이다. 본 연구실에서는 이미 nitride 물질을 기반으로 한 여러 ReRAM 소자들을 제안해 왔다. 그 중 AlN-based ReRAM 소자는 빠른 동작 속도와 좋은 내구성을 보인 바 있다. 하지만 상업화를 위해서 해결해야 할 문제점들이 아직 존재하고 있다. 대표적으로 소자의 배열에서 각 소자의 균일한 동작이 보증되어야 하기 때문에 소자의 셋/리셋 전압의 산포를 줄이고 동작 전류 레벨을 낮추어야 할 필요성이 존재한다. 이러한 ReRAM의 이슈를 해결하기 위해, 본 실험에서는 기존의 AlN-based ReRAM 소자에 Ti를 도핑 방법을 이용하여 소자의 동작 전압 및 전류의 산포를 줄이기 위한 연구를 진행 하였다. 본 실험은 co-sputtering 방법을 이용하여 Ti가 도핑된 AlN을 저항변화 물질로 사용하여 그 특성을 살펴보았다. Ti의 도핑 효과로 소자의 신뢰성 향상 및 동작 전압의 감소 등의 효과를 얻을 수 있었다. 이는 nitride 기반 물질에서 Ti dopant에 의해 형성된 TiN의 효과로 설명된다. TiN는 metallic한 특성을 지니고 있기에 저항변화물질 내에서 일종의 metallic particle의 역할을 수행할 수 있다. 따라서 conducting path의 형성과정에서 이러한 particle 들이 전계를 유도하여 좀 더 균일한 set/reset 특성을 나타내게 된다.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.370.1-370.1
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• 2014

Giant magnetoresistance (GMR), tunneling magnetoresistance (TMR), and magnetic random-access memory (MRAM) are currently active areas of research. Magnetite, Fe3O4, is predicted to possess as half-metallic nature, ~100% spin polarization (P), and has a high Curie temperature (TC~850 K). On the other hand, Spinel ferrite CoFe2O4 has been widely studies for various applications such as magnetorestrictive sensors, microwave devices, biomolecular drug delivery, and electronic devices, due to its large magnetocrystalline anisotropy, chemical stability, and unique nonlinear spin-wave properties. Here we have investigated the magneto-transport properties of epitaxial CoxFe3-xO4 thin films. The epitaxial CoxFe3-xO4 (x=0; 0.4; 0.6; 1) thin films were successfully grown on MgO (100) substrate by molecular beam epitaxy (MBE). The quality of the films during growth was monitored by reflection high electron energy diffraction (RHEED). From temperature dependent resistivity measurement, we observed that the Werwey transition (1st order metal-insulator transition) temperature increased with increasing x and the resistivity of film also increased with the increasing x up to $1.6{\Omega}-cm$ for x=1. The magnetoresistance (MR) was measured with magnetic field applied perpendicular to film. A negative transverse MR was disappeared with x=0.6 and 1. Anomalous Hall data will be discussed.