• 대한임베디드공학회논문지
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• 제13권3호
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• pp.125-131
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• 2018

STT-RAM is attracting as a next generation Non-volatile memory for replacing cache memory with low leakage energy, high integration and memory access performance similar to SRAM. However, there is problem of write operations as the other Non_volatile memory. Hybrid cache memory using SRAM and STT-RAM is attracting attention as a cache memory structure with lowe power consumption. Despite this, reducing the leakage energy consumption by the STT-RAM is still lacking access to the Dynamic energy. In this paper, we proposed as energy management method such as a way-selection approach for hybrid L2 cache fo SRAM and STT-RAM and memory selection method of write/read operation. According to the simulation results, the proposed hybrid cache memory reduced the average energy consumption by 40% on SPEC CPU 2006, compared with SRAM cache memory.

• Transactions on Electrical and Electronic Materials
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• 제16권6호
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• pp.293-302
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• 2015

Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2005년도 한국컴퓨터종합학술대회 논문집 Vol.32 No.1 (A)
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• pp.868-870
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• 2005

최근에는 자원이 제한적인 시스템을 위한 embedded JVM 환경에서 자바 응용 프로그램을 수행할 때 embedded JVM 의 성능에 따른 performance 뿐만 아니라 에너지 소비를 줄이는 일이 크게 대두되고 있다. 메모리에서 사용되는 에너지는 메모리에 접근할 때마다 소비되는 dynamic energy와 메모리에 파워가 들어와 있을 때 항상 소비되는 leakage energy 로 구분할 수 있다. embedded 환경을 고려하지 않았던 이전에는 leakage energy 가 중요한 부분으로 인식되지 않았지만, 현재는 dynamic energy 못지 않게 중요한 부분으로 인식되고 있다. 본 논문에서는 Banked Memory System을 사용하는 임베디드 JVM의 환경하에서 leakage energy를 효과적으로 줄일 수 있는 KVM의 힙 메모리 관리체계를 설계하였다.

• International Journal of Internet, Broadcasting and Communication
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• 제10권4호
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• pp.6-11
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• 2018

As embedded memory technology evolves, the traditional Static Random Access Memory (SRAM) technology has reached the end of development. For deepening the manufacturing process technology, the next generation memory technology is highly required because of the exponentially increasing leakage current of SRAM. Non-volatile memories such as STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory), PCM (Phase Change Memory) are good candidates for replacing SRAM technology in embedded memory systems. They have many advanced characteristics in the perspective of power consumption, leakage power, size (density) and latency. Nonetheless, nonvolatile memories have two major problems that hinder their use it the next-generation memory. First, the lifetime of the nonvolatile memory cell is limited by the number of write operations. Next, the write operation consumes more latency and power than the same size of the read operation.These disadvantages can be solved using the compiler. The disadvantage of non-volatile memory is in write operations. Therefore, when the compiler decides the layout of the data, it is solved by optimizing the write operation to allocate a lot of data to the SRAM. This study provides insights into how these compiler and architectural designs can be developed.

• IEIE Transactions on Smart Processing and Computing
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• 제2권4호
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• pp.226-239
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• 2013

A number of systems have several on-chip memories with cache memory being one of them. Conventional cache memory consists of SRAM but the ratio of static energy to the total energy of the memory architecture becomes larger as the leakage power of traditional SRAM increases. Spin-Torque Transfer RAM (STT-RAM), which is a variety of Non-Volatile Memory (NVM), has many advantages over SRAM, such as high density, low leakage power, and non-volatility, but it consumes too much writing energy. This study evaluated a wide range of energy consumptions of a two-level cache using NVM partially on a mobile processor. Through a number of experimental evaluations, it was confirmed that the use of NVM partially in the two-level cache effectively reduces energy consumption significantly.

• 대한전자공학회논문지TC
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• 제49권7호
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• pp.71-79
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• 2012

컴퓨터 기술이 발전함에 따라 스마트폰, 태블릿 PC 등의 보급이 확산되고 디지털 매체로의 접근이 용이해졌다. 컴퓨터의 하드웨어 성능이 향상되고, 하드웨어 형태의 변화가 발생하였지만 기본적으로 이루어지는 동작 매커니즘의 변화는 이루어지지 않았다. 일반적으로 컴퓨터의 프로그램이 동작하게 되면 프로그램에서 사용하는 데이터가 메모리에 상주하게 된다. 이러한 데이터는 운영체제 동작의 효율성 때문에 메모리에 남아있게 되나, 메모리 덤프나 실시간 메모리 분석을 통해 메모리 내의 데이터에 접근이 가능하다. 이 데이터를 악용할 경우 사용자의 개인정보나 암호화 키, 기밀 데이터 등이 유출될 수 있기 때문에 대응 방안이 마련되어야 한다. 본 논문에서는 가상 메모리의 주소를 이용해 해당 프로세스의 물리 메모리 주소를 찾아내고 해당 프로세스의 메모리 데이터 초기화를 이용하여 사용자의 데이터 유출을 최소화하는 방안을 제안한다.

• 한국컴퓨터정보학회논문지
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• 제23권4호
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• pp.81-88
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• 2018

In this paper, we present some problems with the Groupware Messenger functionality based on dot net 2.0 and implement a new design structure to solve them. They include memory leakage, slow processing, and client window memory crash. These problems resulted in the inconvenience of using instant messaging and the inefficient handling of office tasks. Therefore, in this paper, instant messaging functionality is implemented according to a new design architecture. The new system upgrades dot net 4.5 for clients and deploys the new features based on MQTT for the messenger server. We verify that the memory leak problem and client window memory crash issues have been eliminated on the system with the new messenger functionality. We measure the amount of time it takes to bind data to a set of messages and evaluate the performance, compared to a given system. Through this comparative evaluation, we can see that the new system is more reliable and performing.

• 대한전자공학회논문지SD
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• 제49권8호
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• pp.10-15
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• 2012

본 논문에서는 파워게이팅과 전압레벨조절을 이용하여 누설전류를 줄인 SRAM을 제안하였다. 제안된 파워게이팅 기법은 데이터를 저장하지 않은 메모리 셀 블록의 전력공급을 차단함으로써 누설전류를 크게 감소시키고, 제안된 전압레벨조절 기법은 데이터가 저장된 메모리 셀 블록의 접지전압을 올림으로써 누설전류를 줄여준다. $4K{\times}8$비트 SRAM 칩은 $0.13{\mu}m$ CMOS 공정으로 제작되었고 VDD=1.2V로 동작하였다. 메모리 사용률이 0~100%에 대하여, 동작 모드에서의 누설전류는 $1.23{\sim}9.87{\mu}W$이고 대기 모드에서 누설전류는 $1.23{\sim}3.01{\mu}W$였다. 대기 모드 동안에, 제안된 SRAM의 누설전류는 기존의 SRAM의 12.5~30.5%로 감소하였다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2015년도 춘계학술대회
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• pp.522-524
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• 2015

USB 메모리는 휴대형 보조기억장치로써 보편화되어 있다. 그러나 USB 메모리는 사용 중 분실 및 도난에 의하여 개인정보유출이 문제가 되고 있다. 따라서 재구매가 늘어나고 정보유출에 의한 개인 및 기업들의 피해사례가 늘고 있다. 따라서, 본 논문에서는 스마트 폰과 블루투스로 연동하여 USB 분실을 방지하고, 분실 시 보안 기능을 지원 할 수 있는 Bluetooth 기반 스마트 USB 메모리 시스템을 제안한다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.388-388
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• 2012

In this letter, We have investigated cell characteristics of the alloy FePt-NDs charge trapping memory capacitors with high-k $Al_2O_3$ dielectrics as a blocking oxide. The capacitance versus voltage (C-V) curves obtained from a representative MOS capacitor embedded with FePt-NDs synthesized by the post deposition annealing (PDA) treatment process exhibit the window of flat-band voltage shift, which indicates the presence of charge storages in the FePt-NDs. It is shown that NDs memory with high-k $Al_2O_3$ as a blocking oxide has performance in large memory window and low leakage current when the diameter of ND is below 2 nm. Moreover, high-k $Al_2O_3$ as a blocking oxide increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer. From this result, this device can achieve lower P/E voltage and lower leakage current. As a result, a FePt-NDs device with high-k $Al_2O_3$ as a blocking oxide obtained a~7V reduction in the programming voltages with 7.8 V memory.