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http://dx.doi.org/10.4313/TEEM.2015.16.6.293

FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability  

Salahuddin, Shairfe Muhammad (Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology)
Kursun, Volkan (Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology)
Jiao, Hailong (Department of Electrical Engineering, Eindhoven University of Technology)
Publication Information
Transactions on Electrical and Electronic Materials / v.16, no.6, 2015 , pp. 293-302 More about this Journal
Abstract
Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology.
Keywords
FinFET devices; Underlap; SRAM cell; Memory cache; Data stability; Write voltage margin;
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