• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.21-21
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• 2003

To increase the light-emission efficiency of LED, we increased the internal and external quantum efficiency by suppressing the defect formation in the quantum well and by increasing the light extraction efficiency in LED, respectively. First, the internal quantum efficiency was improved by investigating the effect of a low temperature (LT) grown p-GaN layer on the In$\sub$0.25/GaN/GaN MQW in green LED. The properties of p-GaN was optimized at a low growth temperature of 900oC. A green LED using the optimized LT p-type GaN clearly showed the elimination of blue-shift which is originated by the MQW damage due to the high temperature growth process. This result was attributed to the suppression of indium inter-diffusion in MQW layer as evidenced by XRD and HR-TEM analysis. Secondly, we improved the light-extraction efficiency of LED. In spite of high internal quantum efficiency of GaN-based LED, the external quantum efficiency is still low due to the total internal reflection of the light at the semiconductor-air interface. To improve the probability of escaping the photons outside from the LED structure, we fabricated nano-sized cavities on a p-GaN surface utilizing Pt self-assembled metal clusters as an etch mask. Electroluminescence measurement showed that the relative optical output power was increased up to 80% compared to that of LED without nano-sized cavities. I-V measurement also showed that the electrical performance was improved. The enhanced LED performance was attributed to the enhancement of light escaping probability and the decrease of resistance due to the increase in contact area.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.63-66
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• 1999

We fabricated ramp-edge Josephson junctions with barriers formed by interface treatments instead of epitaxially grown barrier layers. Low-dielectric Sr$_2AITaO_6$(SAT) layer was used as an ion-milling mask as well as an insulating layer for the ramp-edge junctions. An ion-milled YBa$_2Cu_3O_{7-x}$ (YBCO)-edge surface was not exposed to solvent through all fabrication procedures. The barriers were produced by structural modification at the bottom YBCO edge using plasma treatment prior to deposition of the top YBCO electrode. We investigated the effects of pre-annealing and post-annealing on the characteristics of the interface-treated Josephson junctions. The junction parameters were improved by using in-situ RF plasma cleaning treatment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.190-193
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• 2002

The processing technology of organic thin-film transistors (Ons) performances have improved fur the last decade. Gate insulator layer has generally used inorganic layer, such as silicon oxide which has properties of a low electrical conductivity and a high breakdown field. However, inorganic insulating layers, which are formed at high temperature, may affect other layers termed on a substrate through preceding processes. On the other hand, organic insulating layers, which are formed at low temperature, dose not affect pre-process. Known wet-processing methods for fabricating organic insulating layers include a spin coating, dipping and Langmuir-Blodgett film processes. In this paper, we propose the new dry-processing method of organic gate dielectric film in field-effect transistors. Vapor deposition polymerization (VDP) that is mainly used to the conducting polymers is introduced to form the gate dielectric. This method is appropriate to mass production in various end-user applications, for example, flat panel displays, because it has the advantages of shadow mask patterning and in-situ dry process with flexible low-cost large area displays. Also we fabricated four by four active pixels with all-organic thin-film transistors and phosphorescent organic light emitting devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.48-55
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• 2010

As the complexity and the clock speed of semiconductor integrated circuits increase, silicon validation becomes important. In this research, we developed new post-silicon repair & revision techniques to reduce cost and time-to-market. Spare cells are fabricated with the original design and are used for repair when necessary. The interconnections are modified by repair layer revision. The repair cost can be reduced by logic partitioning. Experimental results show that these techniques are effective for low-cost and fast turnaround repair.

• Journal of the Korean Society for Precision Engineering
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• v.24 no.8 s.197
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• pp.138-143
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• 2007

Microstereolithography technology is similar to the conventional stereolithography process and enables to fabricate a complex 3D microstructure. This is divided into scanning and projection type according to aiming at precision and fabrication speed. The scanning MSL fabricates each layer using position control of laser spot on the resin surface, whereas the projection MSL fabricates one layer with one exposure using a mask. In the projection MSL, DMD used to generate dynamic pattern consists of $1024{\times}768$ micromirrors which have $13.68{\mu}m$ per side. The fabrication range and resolution are determined by the field of view of the DMD and the magnification of the projection lens. If using the projection lens with high power, very fine microstructures can be fabricated. In this paper, the projection MSL system adapted to a large surface for array-type fabrication is presented. This system covers the meso range, which is defined as the intermediate range between micro and macro, with a resolution of a few ${\mu}m$. The fabrication of array-type microstructures has been demonstrated to verify the performance of implemented system.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.341.1-341.1
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• 2014

In the advanced material for the next generation display device, transparent amorphous oxide semiconductors (TAOS) are promising materials as a channel layer in thin film transistor (TFT). The TAOS have many advantages for large-area application compared with hydrogenated amorphous silicon TFT (a-Si:H) and organic semiconductor TFT. For the reasonable characteristics of TAOS, The a-IGZO has the excellent performances such as low temperature fabrication (R.T~), high mobility, visible region transparent, and reasonable on-off ratio. In this study, we investigated how the electric characteristics and physical properties are changed as various oxygen ratio when magnetron sputtering. we analysis a-IGZO film by AFM, EDS and I-V measurement. decreasing the oxygen ratio, the threshold voltage is shifted negatively and mobility is increasing. Through this correlation, we confirm the effect of oxygen ratio. We fabricated the bottom-gate a-IGZO TFTs. The gate insulator, SiO2 film was grown on heavily doped silicon wafer by thermal oxidation method. a-IGZO channel layer was deposited by RF magnetron sputtering. and the annealing condition is $350^{\circ}C$. Electrode were patterned Al deposition through a shadow mask(160/1000 um).

• Applied Microscopy
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• v.42 no.4
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• pp.207-211
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• 2012

We examined the electrical properties and microstructure of NiO produced using a sol-gel method and Ni nitrate hexahydrate ($Ni[NO_3]_2{\cdot}6H_2O$) to investigate if this NiO thin film can be used as an insulator layer for resistance random access memory (ReRAM) devices. It was found that as-prepared NiO film was polycrystalline and presented as the nonstoichiometric compound $Ni_{1+x}O$ with Ni interstitials (oxygen vacancies). Resistances-witching behavior was observed in the range of 0~2 V, and the low-resistance state and high-resistance state were clearly distinguishable (${\sim}10^3$ orders). It was also demonstrated that NiO could be patterned directly by KrF eximer laser irradiation using a shadow mask. NiO thin film fabricated by the sol-gel method does not require any photoresist or vacuum processes, and therefore has potential for application as an insulating layer in low-cost ReRAM devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.5
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• pp.371-375
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• 2000

In this paper a new conductivity modulated power transistor called the Lateral Insulated Gated Bipolar Transistor which included n+ ring and p-channel gate is presented. A new lateral IGBT structure is proposed to suppress latch-up and to improve turn off time by imploying n+ ring and p-channel gate and verified by MEDICI. The simulated I-V characteristics at $V_{G}$=15V show that the latch up occurs at $V_{A}$=18V and 6.9$\times$10$^{-5}$ A/${\mu}{\textrm}{m}$ for the proposed LIGBT while the conventional LIGBT latches at $V_{A}$=1.3V and 1.96${\mu}{\textrm}{m}$10$^{-5A}$${\mu}{\textrm}{m}$. It is shown that turn off characteristic of new LIGBT is 8 times than that of conventional LIGBT. And noble LIGBT is not n+ buffer layer because that It includes p channel gate and n+ ring. Therefore Mask for the buffer layer isn’t needed. The concentration of n+ ring is and the numbers of n+ ring and p channel gate are three for the optimal design.n.n.n.n.

• Korean Journal of Materials Research
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• v.16 no.10
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• pp.619-623
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• 2006

Selective vapor deposition of conductive poly(3,4-ethylenedioxythiophene) (PEDOT), thin films has been carried out on self assembled monolayers patterned oxide substrate. Since the 3,4-ethylenedioxythiophene(EDOT) monomer can be polymerized only in the presence of oxidant such as $FeCl_3$, the PEDOT thin film is selectively deposited on patterned $FeCl_3$, which only adsorbs on the partly removed SAMs region due to the inability of $FeCl_3$ to adsorb on SAMs. Therefore, the partly removed SAMs can act as an adsorption layer for the $FeCl_3$ and also as a glue layer for the deposition of PEDOT, resulting in the significantly increased adhesion of PEDOT to $SiO_2$ substrate. The use of UV lithography and Cr patterned quartz mask provided the formation of SAMs patterns on oxide substrates, which allowed for the selective deposition of conductive PEDOT thin films.$^{oo}The$ new process was successfully developed for the selective deposition of PEDOT thin films on SAMs patterned oxide substrate, providing a new way for the patterning of vapor phase deposition of PEDOT thin films with accurate alignment and addressing the inherent adhesion issues between PEDOT and dielectrics.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.742-750
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• 2018

In this paper, in order to enable zero-layer FTP cell using only 5V MOS devices on the basis of $0.13{\mu}m$ BCD process, the tunnel oxide thickness is used as the gate oxide thickness of $125{\AA}$ of the 5V MOS device at 82A. The HDNW layer, which is the default in the BCD process, is used. Thus, the proposed zero layer FTP cell does not require the addition of tunnel oxide and DNW mask. Also, from the viewpoint of memory IP design, a single memory structure which is used only for trimming analog circuit of PMIC chip is used instead of the dual memory structure dividing into designer memory area and user memory area. The start-up circuit of the BGR (Bandgap Reference Voltage) generator circuit is designed to operate in the voltage range of 1.8V to 5.5V. On the other hand, when the 64-bit FTP memory IP is powered on, the internal read signal is designed to maintain the initial read data at 00H. The layout size of the 64-bit FTP IP designed using the $0.13-{\mu}m$ Magnachip process .is $485.21{\mu}m{\times}440.665{\mu}m$($=0.214mm^2$).