• Proceedings of the Korea Society for Industrial Systems Conference
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• 1999.05a
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• pp.53-57
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• 1999

본 논문에서는 입출력간의 연관관계가 트리구조로 표현되는 DTG(Directed tree graph)에 의한 고속병렬다치논리회로를 설계하는 알고리즘과 DTG의 각 절점에 코드를 할당하는 알고리즘을 제안한다. 임의의 절점을 갖는 DTG에 대하여 본 논문에서는 절점들이 매개변수에 의하여 표현될 때 양의 정수로 표현되도록 논리레벨 P를 할당하고 각 레벨에 각기 다른 잉여절점을 추가하여 회로를 설계한다. 또한, 절점들의 입출력 관계를 단지 하나의 매개변수 m$_{i}$를 이용하여 전달행렬 A를 구하기 때문에 더 빠르고 간단하게 회로를 설계할 수 있다. 본 논문에서 제안한 알고리즘은 Nakajima 등에 의해 제안된 알고리즘으로는 설계가 가능하지 않았던 임의의 절점을 가지는 DTG에 대해서도 회로를 설계할 수 있는 장점이 있다. 또한, 자연수 내에서 선형성, 정규성, 및 가시적인 장점을 가지며 절점수의 감소를 통한 처리속도의 향상, 회로 구성의 간략화 및 비용절감등의 장점등이 있다.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.741-744
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• 1999

In this paper, We represent a low complexity of parallel canonical basis multiplier for GF( q$^{n}$ ), ( q＞ 2). The Mastrovito multiplier is investigated and applied to multiplication in GF(q$^{n}$ ), GF(q$^{n}$ ) is different with GF(2$^{n}$ ), when MVL is applied to finite field. If q is larger than 2, inverse should be considered. Optimized irreducible polynomial can reduce number of operation. In this paper we describe a method for choosing optimized irreducible polynomial and modularizing recursive polynomial operation. A optimized irreducible polynomial is provided which perform modulo reduction with low complexity. As a result, multiplier for fields GF(q$^{n}$ ) with low gate counts. and low delays are constructed. The architectures are highly modular and thus well suited for VLSI implementation.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.275-278
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• 2003

This paper presents a full-adder using current-mode multiple valued logic CMOS circuits. This paper compares propagation delay, power consumption, and PDP(Power Delay Product) compared with conventional circuit. This circuit is designed with a samsung 0.35um n-well 2-poly 3-metal CMOS technology. Designed circuits are simulated and verified by HSPICE. Proposed full-adder has 2.25 ns of propagation delay and 0.21 mW of power consumption.

• Journal of Sensor Science and Technology
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• v.33 no.3
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• pp.147-151
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• 2024

The importance of Wireless Sensor Networks is becoming more evident owing to their practical applications in various areas. However, the energy problem remains a critical barrier to the progress of WSNs. By reducing the energy consumed by the sensor nodes that constitute WSNs, the performance and lifespan of WSNs will be enhanced. In this study, we introduce an energy-efficient ternary modulator that employs multi-threshold CMOS for logic conversion. We optimized the design with a low-power ternary gate structure based on a pass transistor using the MTCMOS process. Our design uses 71.69% fewer transistors compared to the previous design. To demonstrate the improvements in our design, we conducted the HSPICE simulation using a CMOS 180 nm process with a 1.8V supply voltage. The simulation results show that the proposed ternary modulator is more energy-efficient than the previous modulator. Power-delay product, a benchmark for energy efficiency, is reduced by 97.19%. Furthermore, corner simulations demonstrate that our modulator is stable against PVT variations.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.6
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• pp.2632-2640
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• 2012

The purpose of this study was to investigate whether medial gastrocnemius ultrasound imaging of the Delayed Onset Muscle Soreness (DOMS) has the possibilities as a measurement method. This study was conducted from April 21th 2011 to April 30th 2011. Thirty-five healthy subjects were included based on the absence of regular physical activity, and no history of recent trauma, musculoskeletal pathology, cardiovascular disease or drug intake. All subjects induced DOMS through climbing for 5 hours and we measured the visual analogue scale (VAS), creatine kinase (CK) and maximal voluntary isometric contraction (MVlC) of ankle plantar flexor prior to DOMS and at 24, 48 and 72 hours post DOMS and these measurements were compared with pennation angle of medial gastrocnemius measured by ultrasound imaging. Results of this study were as following. VAS, CK, and MVIC of ankle plantar flexor were found significant difference related measurement period (p<0.05) and pennation angle of medial gastrocnemius were found significant difference related measurement period (p<0.05). Furthermore, we confirmed that the flow of change between variables related measurment period was consistent. Through this study, we think that measuring the changes in pennation angle of medial gastrocnemius over time using ultrasound imaging will be able to be used as a new method measuring DOMS.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.3
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• pp.102-109
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• 2001

In this paper, a new multiplication algorithm which describes the methods of constructing a multiplierover GF(p$^{m}$ ) was presented. For the multiplication of two elements in the finite field, the multiplication formula was derived. Multiplier structures which can be constructed by this formula were considered as well. For example, both GF(3) multiplication module and GF(3) addition module were realized by current-mode CMOS technology. By using these operation modules the basic cell used in GF(3$^{m}$ ) multiplier was realized and verified by SPICE simulation tool. Proposed multipliers consisted of regular interconnection of simple cells use regular cellular arrays. So they are simply expansible for the multiplication of two elements in the finite field increasing the degree m.

• Journal of the Korean Institute of Intelligent Systems
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• v.16 no.6
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• pp.659-664
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• 2006

The Context-Aware system is the core technology in the Ubiquitous Computing Environment. Recently, the practical use of a sensor is magnified and the application fields of it are gradually extended in order to collect necessary context information. Context-Aware service integrates the context information which is collected by sensors, and then provides, a suitable service to a user through the process of analysis and reasoning. This service is studied in a variety of fields such as marketing, medical treatment, education and so on. In this paper, we analyze the method of recognizing surrounding context and the result of the awareness by using differential and structural property of multiple valued logic function; propose the model that provides appropriate service depending on the change of surrounding contort; confirm the applicability of the Context-aware system by showing the example of application.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.152-162
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• 2003

In this paper, Binary to Quaternary Converter(BQC), Quaternary to Binary Converter(QBC) and Quaternary inverter circuit, which is the basic logic gate, have been proposed based on voltage mode. The BQC converts the two bit input binary signals to one digit quaternary output signal. The QBC converts the one digit quaternary input signal to two bit binary output signals. And two circuits consist of Down-literal circuit(DLC) and combinational logic block(CLC). In the implementation of quaternary inverter circuit, DLC is used for reference voltage generation and control signal, only switch part is implemented with conventional MOS transistors. The proposed circuits are simulated in 0.35 ${\mu}{\textrm}{m}$ N-well doubly-poly four-metal CMOS technology with a single +3V supply voltage. Simulation results of these circuit show 250MHz sampling rate, 0.6mW power consumption and maintain output voltage level in 0.1V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.52-62
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• 2003

This paper discusses ternary logic gate, ternary D flip-flop, and ternary four-digit parallel input/output register. The ternary logic gates consist of n-channel pass transistors and neuron MOS(νMOS) threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The νMOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level νMOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. The ternary four-digit parallel input/output register consists of four ternary D flip-flops which can temporarily store four-digit ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35m process parameter, and also represent HSPICE simulation result.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.7
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• pp.4891-4896
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• 2015

In this paper planed Secret Single Message Service using MVLS(Multipurpose Visual Language System) for conceal contents to other persons that based on national institutions and private organizations report. This system is not persue to important contents like national or company's secret, but merely just decode to general and conceal SMS that using peoples at real life. This system is have an advantage that encoding to message like between lover's conversations or dislike contents to view the other persons, only can see own users that is to keep private life. Also, this system offers convenience to users that using general SMS service and only activate On-Off function for secret mode to user's needs.