A Study on Irreducible Polynomial for Construction of Parallel Multiplier Over GF(q$^{n}$ )

GF($q^n$)상의 병렬 승산기 설계를 위한 기약다항식에 관한 연구

  • 오진영 (인하대학교 전자공학과) ;
  • 김상완 (인하대학교 전자공학과) ;
  • 황종학 (인하대학교 전자공학과) ;
  • 박승용 (인하대학교 전자공학과) ;
  • 김홍수 (인하대학교 전자공학과)
  • Published : 1999.06.01

Abstract

In this paper, We represent a low complexity of parallel canonical basis multiplier for GF( q$^{n}$ ), ( q> 2). The Mastrovito multiplier is investigated and applied to multiplication in GF(q$^{n}$ ), GF(q$^{n}$ ) is different with GF(2$^{n}$ ), when MVL is applied to finite field. If q is larger than 2, inverse should be considered. Optimized irreducible polynomial can reduce number of operation. In this paper we describe a method for choosing optimized irreducible polynomial and modularizing recursive polynomial operation. A optimized irreducible polynomial is provided which perform modulo reduction with low complexity. As a result, multiplier for fields GF(q$^{n}$ ) with low gate counts. and low delays are constructed. The architectures are highly modular and thus well suited for VLSI implementation.

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