• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.197-204
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• 2002

DRAM, SRAM, and FLASH memory are three major memory devices currently used in most electronic applications. But, they have very distinct attributes, therefore, each memory could be used only for limited applications. MRAM (Magneto-resistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-volatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnel Junction) as a data storage part and MOS transistor as a data selection part. To be a commercially competitive memory device, scalability is an important factor as well. This paper is testing the actual electrical parameters and the scaling factors to limit MRAM technology in the semiconductor based memory device by an actual integration of MRAM core cell. Electrical tuning of MOS/MTJ, and control of resistance are important factors for data sensing, and control of magnetic switching for data writing.

• Journal of Magnetics
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• v.7 no.3
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• pp.101-105
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• 2002

MRAM (Magnetoresistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-volatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnel Junction) as a data storage part and MOS transistor as a data selection part. This paper is for testing the actual electrical parameters to adopt MRAM technology in the semiconductor based memory device. The discussed topics are an actual integration of MRAM core cell and its properties such as electrical tuning of MOS/MTJ for data sensing and control of magnetic switching for data writing. It will be also tested that limits of the MRAM technology for a high density memory.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.31-38
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• 2016

A novel self-reference sense amplifier with parallel reading during writing operation is proposed. Read access time is improved compared to conventional self-reference scheme with fast operation speed by reducing operation steps to 1 for read operation cycle using parallel reading scheme, while large sense margin competitive to conventional destructive scheme is obtained by using self-reference scheme. The simulation was performed using standard $0.18{\mu}m$ CMOS process. The proposed self-reference sense amplifier improved not only the operation speed of less than 20 ns which is comparable to non-destructive sense amplifier, but also sense margin over 150 mV which is larger than conventional sensing schemes. The proposed scheme is expected to be very helpful for engineers for developing MRAM technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.105-113
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• 2004

MRAM uses magneto-resistance material as a storage element, which stores cell data as a polarization of spin in a free magnetic layer. This magneto-resistance material has hysteresis, asteroid curve at the thermal variation, and R-V characteristics for switching the data. Therefore, a macro-model which can reproduce these characteristics is required for MRAM simulation. We propose a macro-model of TMR (Tunneling Magneto Resistance) that can reproduce all of these characteristics on HSPICE. Also we propose a novel sensing scheme, which generates reference resistance having the medium value, ( $R_{H}$+ $R_{L}$)/2, for a wide range of applied voltage and present simulation results based on the HSPICE macro-model of MTJ that we have developed.d.d.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.863-866
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• 2003

Recently, there has been growing interests in the magneto-resistive random access memory (MRAM) because of its great potential as a future nonvolatile memory. In this paper, a CMOS macro-model for MRAM cell based on a twin cell structure is proposed. The READ and WRITE operations of the MTJ cell can be emulated by adopting data latch and switch blocks. The behavior of the circuit is confirmed by HSPICE simulations in a 0.35-${\mu}{\textrm}{m}$ CMOS process. We expect the macro model can be utilized to develope the core architecture and the peripheral circuitry. It can also be used for the characterization and the direction of the real MTJ cells.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2009.05a
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• pp.110-110
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• 2009

최근 차세대 비휘발성 메모리(NVM) 기술은 메모리의 성능과 기존의 한계점을 효과적으로 극복하며 활발한 연구를 통해 비약적으로 발전하고 있으며 특히, phase-change random access memory (PRAM)은 ferroelectric random access memory (FeRAM)과 magneto-resistive random access memory (MRAM)과 같은 다른 NVM 소자와 비교하여 기존의 DRAM과 구조적으로 비슷하고 상용화가 빠르게 진행될 수 있을 것으로 예상되는 바, PRAM에 사용되는 상변화 물질의 식각을 수행하고 X-ray photoelectron spectroscopy (XPS)를 통해 표면의 열화현상을 관찰하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.110-116
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• 2004

We propose a novel sensing scheme, which operates by sensing the difference in voltage between a memory cell and a reference cell for a magneto-resistive random access memory (MRAM). A new midpoint-reference generation circuit is adopted for the reference cell to improve the sensing margin and to guarantee correct operation of sensing circuit for wide range of tunnel magneto resistance (TMR) voltages. In this scheme, the output voltage of the reference cell becomes nearly the midpoint between the cell voltages of high and low states even if the voltage across the magnetic tunnel junction (MTJ) varies.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.815-818
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• 2003

New sensing and writing schemes for a magneto-resistive random access memory (MRAM) with a twin cell structure are proposed. In order to enhance the cell reliability, a scheme of the low voltage precharge is employed to keep the magneto resistance (MR) ratio constant. Moreover, a common gate amplifier is utilized to provide sufficient voltage signal to the bit line sense amplifiers under the small MR ratio structures. To enhance the writing reliability, a current mode technique with tri-state current drivers is adopted. During write operations, the bit and /bit lines are connected. And 'HIGH' or 'LOW' data is determined in terms of the current direction flowing through the MTJ cell. With the viewpoint of the improved reliability of the cell behavior and sensing margin, HSPICE simulations proved the validity of the proposed schemes.

• Journal of KIISE
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• v.42 no.3
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• pp.379-389
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• 2015

With the advent of non-volatile memories such as Phase Change Memory (PCM or PRAM) and Magneto Resistive RAM (MRAM), active studies have been carried out on how to replace Dynamic Random-Access Memory (DRAM) with PRAM. In this paper, we study both endurance and performance issues of existing join algorithms that are based on PRAM-based computer systems and have been widely used until now: Block Nested Loop Join, Sort-Merge Join, Grace Hash Join, and Hybrid Hash Join. Our experimental results show that the existing join algorithms need to be redesigned to improve both the endurance and performance of PRAMs. To the best of our knowledge, this is the first research to scientifically study the results of the four join algorithms running on PRAM-based systems. In this work, our main contribution is the modeling and implementation of a PRAM-based simulator for a comparative study of the existing join algorithms.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.356.2-356.2
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• 2014

Spin Transfer Torque (STT) is of great interest in data writing scheme for the Magneto-resistive Random Access Memory (MRAM) using Magnetic Tunnel Junction (MTJ). Scalability for high density memory requires ferromagnetic electrodes having the perpendicular magnetic easy axis. We investigated CoZr as the ferromagnetic electrode. It is observed that interfacial magnetic anisotropy is preferred perpendicular to the plane with thickness dependence on the interfaces with Pt layer. The anisotropy energy (Ku) with thickness dependence shows a change of magnetic-easy-axis direction from perpendicular to in-plane around 1.2 nm of CoZr. The interfacial anisotropy (Ki) as the directly related parameters to switching and thermal stability, are estimated as $1.64erg/cm^2$ from CoZr/Pt multilayered system.