• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.29-36
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• 2003

In this paper, an efficient VLSI architecture for DCTQ module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the module is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling 30 frame CIF image for both encoder and decoder simultaneously. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. To reduce the power consumption of DCTQ modu1e, we propose the method not to operate the DCTQ modu1e exploiting the SAE(sum of absolute error) value from motion estimation and cbp(coded block pattern). To reduce the AC/DC prediction memory size, the memory architecture and memory access method for AC/DC prediction block is proposed. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.211-216
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• 2009

As demands for high-definition television (HDTV) increase, the implementation of real-time decoding of high-definition (HD) video becomes an important issue. The data size for HD video is so large that real-time processing of the data is difficult to implement, especially with software. In order to implement a fast moving picture expert group-2 decoder for HDTV, we compose five scenarios that use parallel processing techniques such as data decomposition, task decomposition, and pipelining. Assuming the multi digital signal processor environments, we analyze each scenario in three aspects: decoding speed, L1 memory size, and bandwidth. By comparing the scenarios, we decide the most suitable cases for different situations. We simulate the scenarios in the dual-core and dual-central processing unit environment by using OpenMP and analyze the simulation results.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.355-355
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• 2002

In this paper, we designed a FPU(floating point unit) that it is very important and requires of high density when digital audio is designed. Almost audio system must support the multi-channel and required for high quality. A floating point arithmetic function in MPEG-2 AAC that implemented by hardware is able to realtime decoding when DSP realization. The reason is that MPEG-2 AAC is compatible to the Audio field of MPEG-4 and afterwards. We designed a FPU by hardware to increase the speed of a floating point unit with much calculation part in the MPEG-2 AAC Decoder. A FPU is composed of a multiplier and an adder. A multiplier used the Radix-4 Booth algorithm and an adder adopted 1's complement method for speed up. A form of a floating point unit has 8bit of exponent part and 24bit of mantissa. It's compatible with the IEEE single precision format and adopted a pipeline architecture to increase the speed of a processor. All of sub blocks are based on ISO/IEC 13818-7 standard. The algorithm is tested by C language and the design does by use of VHDL(VHSIC Hardware Description Language). The maximum operation speed is 23.2MHz and the stable operation speed is 19MHz.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.181-184
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• 1999

본 논문에서는 MPEG-1 계층 II와 MPEG-2 계층 II LSF 오디오 복호기를 OAK DSP Core를 이용하여 실시간 응용이 가능하도록 구현하였다. Ungrouping시 이용되는 테이블을 효율적으로 사용하였으며 합성필터부의 RAM과 ROM의 크기 그리고 각 부분의 연산에 필요한 연산량을 최적화하기 위하여 알고리듬을 효율적으로 적용하였고 불필요한 연산 부분을 제거하거나 최적화 하였다.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.481-484
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• 2001

본 논문에서는 MPEG-2 AAC 디코더의 DSP구현에 관한 연구결과로서 IS0/1EC 13818-7 표준에 의거 구현된 MPEC-2 AAC 디코더의 각 세부 기능블럭들의 구성 및 동작원리에 대하여 요약 기술하고. DSP연산에 최적화된 연산구조의 연구를 바탕으로 16bit 고정소수점 연산구조를 가지는 DSP상에서 구현된 MPEG-2 AAC 디로더의 시스템의 하드웨어 및 소프트웨어 구성에 관하여 간략한 기술하였다. 구성된 디코더의 성능평가를 통하여 MPEC-2 AAC 비트스트림을 디코딩하기 위하여 필요로 하는 연산량 및 소요 메모리의 양을 측정하고, 디코더 성능의 중요 척도인 음질평가를 수행하였다. 수행방법으로서 conformance test에 의거하여 PSNR을 측정함으로써 객관적인 성능 지표의 제시와 함께, 주관적인 음질 평가도 병행하여 수행하였다.

• ETRI Journal
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• v.29 no.1
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• pp.103-106
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• 2007

Pilot-based coding (PBC), which is used for lossless bit rate reduction of audio coding, has been recently proposed for MPEG Surround. We propose extended PBC for further lossless bit rate reduction of MPEG Surround. Extended PBC selects the number of pilots depending on the parameter band number and the type of spatial parameter. It then encodes the pilots and the relevant difference data. Experiments show that extended PBC is more effective than the original PBC, especially for high bit rate modes, with a negligible complexity increase on the decoder side.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.4 no.1
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• pp.34-39
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• 2004

Huffman coding which has been used in many data compression algorithms is a popular data compression technique used to reduce statistical redundancy of a signal. It has been proposed that the Huffman algorithm can decode efficiently using characteristics of the Huffman tables and patterns of the Huffman codeword. We propose a new Huffman decoding algorithm which used a multi way tree search and present an efficient hardware implementation method. This algorithm has a small logic area and memory space and is optimized for high speed decoding. The proposed Huffman decoding algorithm can be applied for many multimedia systems such as MPEG audio decoder.

• Proceedings of the IEEK Conference
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• 2000.06d
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• pp.174-177
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• 2000

본 논문에서는 높은 압축률과 고음질을 제공하는 MPEG-1 Layer Ⅲ 오디오 디코더를 고정소수점 DSP인 TMS320C6201을 이용하여 실시간으로 동작하도록 구현하였다. ISO/IEC에서 제공하는 부동소수점 C 프로그램을 음질의 손실 없이 고정소수점 연산으로 변환하었고 실시간 동작을 위하여 최적화 작업을 수행하였다. 연산의 정확성을 높이기 위해서 Descaling 모듈에 중점을 두어 부동소수점 연산을 고정소수점 연산으로 변환하였고 IMDCT 모듈과 Synthesis Polyphase Filter Bank 모듈에 대해 고속 알고리즘을 적용하여 연산량과 프로그램 크기를 크게 줄일 수 있었다. 구현된 디코더는 TMS320C6201 DSP가 수행할 수 있는 최대 연산량의 26%만으로 실시간 동작이 가능하였고 부동소수점 연산 결과와 고정소수점 연산 결과를 비교하여 60 dB 이상의 높은 SNR을 가짐을 확인하였다. 또한 사운드 입출력과 호스트 통신을 통하여 EVM 보드에서 실시간으로 동작함을 확인하였다.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.161-164
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• 2000

본 논문에서는 최근 휴대용 오디오 기기 등에서 활발하게 사용되고 있는 MP3 (MPEG-1,2 계충-III) 오디오 복호화 알고리듬을 실시간 구현하였다. 휴대용 기기에 적합한 저전력 설계를 위하여 16비트 고정 소수점 범용 DSP인 모토로라 DSP56654를 이용하였고, 연산량을 줄이기 위한 작업을 수행하였다. 또한 음질 열화를 최소화하고 CD 수준의 고음질을 얻기 위해서 각 복호화 과정에 대한 최적의 고정소수점 연산을 연구하였다. 구현된 복호화기는 약 40MIPS 정도의 연산량으로 90dB이상의 SNR을 갖는 최종 PCM 샘플을 생성한다.

• ETRI Journal
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• v.44 no.1
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• pp.38-50
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• 2022

This paper presents a study on the use of encoder-derived features in decoder-side depth estimation. The scheme of multiview video encoding does not require the transmission of depth maps (which carry the geometry of a three-dimensional scene) as only a set of input views and their parameters are compressed and packed into the bitstream, with a set of features that could make it easier to estimate geometry in the decoder. The paper proposes novel recursive block splitting for the feature extraction process and evaluates different scenarios of feature-driven decoder-side depth estimation, performed by assessing their influence on the bitrate of metadata, quality of the reconstructed video, and time of depth estimation. As efficient encoding of multiview sequences became one of the main scopes of the video encoding community, the experimental results are based on the "geometry absent" profile from the incoming MPEG Immersive video standard. The results show that the quality of synthesized views using the proposed recursive block splitting outperforms that of the state-of-the-art approach.