• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1065-1068
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• 2003

For the first time, high quality ultra-thin strained Si/SiGe on Insulator (SGOI) substrate with total SGOI thickness( $T_{Si}$ + $T_{SiGe}$) of 13 nm is developed to combine the device benefits of strained silicon and SOI. In the case of 6- 10 nm-thick top silicon, 100-110 % $I_{d,sat}$ and electron mobility increase are shown in long channel nFET devices. However, 20-30% reduction of $I_{d,sat}$ and electron mobility are observed with 3 nm top silicon for the same long channel device. These results clearly show that the FETs operates with higher performance due to the strain enhancement from the insertion of SiGe layer between the top silicon layer and the buried oxide(BOX) layer. The performance degradation of the extremely thin( 3 nm ) top Si device can be attributed to the scattering of the majority carriers at the interfaces.

• 전기의세계
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• 제24권6호
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• pp.35-38
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• 1975

금속과 원소반도체의 접촉으로 이루어진 점접촉트란지스터를 출발점으로 한 P-N접합트란지스터는 4반세기동안 반도체전자 소자의 중심이었다. 이와 같은 반도체소자는 단결정반도체의 특성을 이용한 것으로 그 제작에 있어 거의 완전에 가까운 결정구조와 극도의 화학적순수성이 요구되는 것이다. 이와 같은 요구조건은 접합형 반도체소자제작에 큰 제한을 주게 된다. Gunn Diode, Impatt Diode등으로 반도체소자는 Bulk형식의 것이 각광을 받게 되었으며 MOS형식의 FET에 이르러 신기원을 이루게 되었다. 이리하여 MOS기술은 Sapphire기반을 도입함으로써 SOS기법으로 발전을 거듭하게 되었다. 그러나 정질반도체의 이용이라는 근본적 개념에서는 이탈치못하고 있다. 이상과 같은 정질반도체소자에 대응하여 반대적 입장에서 불순물농도의 영향이 적은 비정질반도체의 연구가 70년이후 미국을 중심으로 활발하게 전개되고 있다. 그 연구 및 개발결과는 2년마다 이루어지는 액체비정질반도체국제회의에서 종합되고 있다. 이 분야에서의 연구는 1968년 Ovshinsky가 비산화물 Chalcogenide glass 비정질박막에서의 빠른 응답속도의 양극대칭성 Switching 현상 발견을 계기로 신국면을 개척하게 된 것이다. 이들 비정질반도체에 대한 물성론적 흥미와 응용면에 관한 기대로부터 전도기구의 해명과 응용회로의 개발연구가 급속히 진전되고 있다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1579-1581
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• 1996

The high temperature characteristics of SOI BMFET are analyzed by the numerical simulation and compared with MOS-gated SOI power devices at high temperatures. The proposed SOI BMFET combines bipolar operation in the on-state with unipolar FET operation in the off-state, so that it may be suitable for high temperature operation without any significant degradation of performance such as the leakage current and blocking capability. The simulation results show that SOI BMFET with a higher doped n-resurf layer is the most promising device far high temperature application as compared with MOS-gated SOI power devices, exhibiting the low on-state voltage drop as well as the excellent forward blocking capability at high temperature.

• 한국전기전자재료학회논문지
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• 제18권1호
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• pp.17-23
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• 2005

The switching characteristics of MOS-Controlled Thyristor(MCT) is studied with variation of the channel length and impurity concentration in ON and OFF FET channel. The proposed MCT power device has the lateral structure and P-epitaxial layer in substrate. Two dimensional MEDICI simulator and PSPICE simulator are used to study the latch-up current and forward voltage-drop from the characteristics of I-V and the switching characteristics with variation of channel length and impurity concentration in P and N channel. The channel length and N impurity concentration of the proposed MCT power device show the strong affect on the transient characteristics of current and power. The N channel length affects only on the OFF characteristics of power and anode current, while the N doping concentration in P channel affects on the ON and OFF characteristics.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 전력전자학술대회 논문집
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• pp.24-26
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• 1998

A new high frequency switching drive method using IGBT is proposed for non-magnetic induction heating system. Using this method, the switching and conduction losses of the switching devices can be reduced. In addition, since IGBT cosl is lower than MOS-FET one, the system cosl can be remarkably pared down. The prototype induction heating system with 1.2㎾ power consumption is builted and tested to verify the operation of the proposed high frequency switching drive method.

• 대한전자공학회논문지
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• 제22권5호
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• pp.102-109
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• 1985

다차원 Monte Carlo방법을 연구하여 새로운 yield 최대화 절차를 연구하였다. 새로 변형된 weight 선택 알고리즘을 MOS FET NAND 게이트에 적용하여 최대 yield추정을 하였다. 또한 본논문의 yield 최대화 절차는 목적함수가 non-convex일때도 적용된다.

• 산업기술연구
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• 제27권B호
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• pp.15-20
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• 2007

This paper presents the new design method for the gate driver circuit of the floating MOSFET by using the pulse transformer. Each parameters of the proposed circuit are delivered by the numerical calculation method. By considering inner characteristics of MOSFET, the gate driver makes to increase the efficiency of the power conversion and decrease operating heat. Computer simulations and to experimental results for a Buck Converter are presented in order to validate the proposed method.

• Transactions on Electrical and Electronic Materials
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• 제14권5호
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• pp.235-241
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• 2013

A low power CMOS control circuit is applied in an integrated DC-DC buck converter. The integrated converter is composed of a feedback control circuit and power block with 0.35 ${\mu}m$ CMOS process. A current-sensing circuit is integrated with the sense-FET method in the control circuit. In the current-sensing circuit, a current-mirror is used for a voltage follower in order to reduce power consumption with a smaller chip-size. The N-channel MOS acts as a switching device in the current-sensing circuit where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time. The converter offers well-controlled output and accurately sensed inductor current. Simulation work shows that the current-sensing circuit is operated with an accuracy of higher than 90% and the transient time of the error amplifier is controlled within $75{\mu}sec$. The sensing current is in the range of a few hundred ${\mu}A$ at a frequency of 0.6~2 MHz and an input voltage of 3~5 V. The output voltage is obtained as expected with the ripple ratio within 1%.

• 센서학회지
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• 제13권2호
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• pp.90-95
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• 2004

Protein and gene detection have been growing importance in medical diagnostics. Field effect transistor (FET) - type biosensors have many advantages such as miniaturization, standardization, and mass-production. In this work, we have fabricated metal-oxide-semiconductor (MOS) FET that operates as molecular recognitions based electronic sensor. Measurements were taken with the devices under phosphate buffered saline solution. The drain current ($I_{D}$) was decreased after forming self-assembled mono-layers (SAMs) used to capture the protein, which resulted from the negative charges of SAMs, and increased after forming protein by 11.5% at $V_{G}$ = 0 V due to the positive charges of protein.

• Applied Microscopy
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• 제41권2호
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• pp.89-98
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• 2011

Atom Probe Tomography는 원자 수준의 분해능으로 원소의 위치 및 조성 정보를 3차원으로 제공해 주는 분석 장비이다. APT의 우수한 성능에도 불구하고 반도체 등, 저전도성 물질 분석에는 그 동안 적용이 어려웠다. 그러나 특정 시료 내 위치의 시편을 가공할 수 있는 FIB 시편 제조법과 laser펄스를 이용한 전계증발법의 개발로 APT의 분석 영역이 반도체에서 절연체까지 크게 확대 되고 있다. 본 논문에서는 최근에 적용되기 시작한 MOS-FET, GaN LED, Si-Nanowire 등 전자소자에서의 APT분석 응용사례에 대하여 살펴보았다.