• Proceedings of the IEEK Conference
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• 2000.11c
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• pp.153-156
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• 2000

A novel silicon retina chip based on the information processing in the vertebrate retina was designed. The chip has a novel wiring structure in which all pixels are connected through the channel of MOS transistors, which simplifies a wiring structure compared with conventional resistive networks. The proposed structure minimizes the pixel area and certainly increases a fill factor since each pixel consists of only two photodiodes and three MOS transistors. It also enables the chip to operate over a wide range of light intensity by adjusting its conductance with the gate voltage. Simulation results with SPICE showed that the chip could extract the edge of input images successfully.

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.90.3-90
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• 1998

• KIEE International Transactions on Electrophysics and Applications
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• v.5C no.2
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• pp.58-62
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• 2005

A trench MOS barrier Schottky (TMBS) rectifier is proposed which utilizes the upper half of the trench sidewall as an active area. The proposed structure improves the forward voltage drop by 20$\%$ in comparison with the conventional one without degradation in breakdown voltage. An analytical model for the field distribution is given and compared with two-dimensional numerical simulations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.205-210
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• 2003

A 3-Transistor cell CMOS OTP ROM array using standard CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option as a high density OTP ROM array for modern digital as well as analog circuits.

• Proceeding of EDISON Challenge
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• 2013.04a
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• pp.252-255
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• 2013

Nano MOS with $Er_2O_3/SiO_2$ double-layer gate dielectrics was demonstrated by EDISON Nanophysics software. Double-layer structure decreases the gate leakage current in two orders compared with $SiO_2$ single-layer gate dielectric.

• Proceedings of the KIEE Conference
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• 1989.07a
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• pp.377-379
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• 1989

Very thin gate oxide(100-300A) MOS capacitor has been fabricated. The effect of series resistance must be calculated and the exact metal-semiconductor work function difference should be obtained to get the fixed oxide charge density exisiting in oxide. Dilute oxidation make sagy to control oxide thickness and reduce fixed oxide charge density. In case of dilute oxidation, fixed oxide charge density depends on oxidation time. If oxide is very thin, the annealing effect is ignored.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.921-926
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• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.10
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• pp.1034-1040
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• 2004

The latch-up current and switching characteristics of MOS-Controlled Thyristor(MCT) are studied with variation of the channel length and impurity concentration. The proposed MCT power device has the lateral structure and P-epitaxial layer in substrate. Two dimensional MEDICI simulator is used to study the latch-up current and forward voltage-drop from the characteristics of I-V and the switching characteristics with variation of impurity concentration. The channel length and impurity concentration of the proposed MCT power device show the strong affect on the anode current and turn-off time. The increase of impurity concentration in P and N channels is found to give the increase of latch-up current and forward voltage-drop.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.788-791
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• 1988

The C-T characteristics of nitridized MOS capacitor have been studied. The generation lifetimes were calculated using C-T transient response ans found to vary as sample condition. This is due to the non-uniformity of fast surface state. Also, This experimental curves were different from theoretical curves. The result suggests that the change in material structure (from SiO2 to Si-N-O) is important in improving minority carrier lifetime.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.4
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• pp.562-567
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• 1996

A new lateral MOS controlled thyristor, named Shorted Anode LMCT(SA-LMCT), is proposed and analyzed by a two-dimensional device simulation. The device structure employs the implanted n+ layer which shorts the p+ anode together by a common metal electrode and provides a electron conduction path during turn-off period. The turn-off is achieved by not only diverting the hole current through the p+ cathode short but also providing the electron conduction path from the n-base into the n+ anode electrode. In addition, the modified shorted anode LMCT, which has an n+ short junction located inside the p+ anode junction, is also presented. It is shown that the modified SA-LMCT enjoys the advantage of no snap-back behavior in the forward characteristics with little sacrificing of the forward voltage drop. The simulation result shows that the turn-off times of SA-LMCT can be reduced by one-forth and the maximum controllable current density may be increased by 45 times at the expense of 0.34 V forward voltage drop as compared with conventional LMCT. (author). 11 refs., 6 figs., 1 tab.