• Title/Summary/Keyword: MOS devices

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A Study on the Energy Distribution of Interface Traps in MOS Devices Under Non-steady-state (비정상상태에 있는 MOS내의 경사면트랩에너지 분포에 관한 연구)

  • Cho, Chul;Kim, Jae-Hoon
    • 전기의세계
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    • v.26 no.6
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    • pp.86-92
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    • 1977
  • The phenomenon of non-steady-state current flow through the interface traps during the dielectric relaxation of MOS device is presented. Experimental method is also described for determining the energy distribution of interface traps, which is based on isothermal dielectric relaxation current technique. Actually, the energy distribution of interface traps was obtained by measuring the transient current through the traps at Si-SiO$_{2}$ interface only in lower-half of the bandgap. It is shown that the trap energy distributio has peak value 1.72*10$^{13}$ cm$^{-2}$ eV$^{-1}$ near 0.73eV approximately.

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Characteristics and Formation of Thermal Oxidative Film Silicon Carbide for MOS Devices (MOS 소자용 Silicon Carbide의 열산화막 생성 및 특징)

  • O, Gyeong-Yeong;Lee, Gye-Hong;Lee, Gye-Hong;Jang, Seong-Ju
    • Korean Journal of Materials Research
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    • v.12 no.5
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    • pp.327-333
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    • 2002
  • In order to obtain the oxidation layer for SiC MOS, the oxide layers by thermal oxidation process with dry and wet method were deposited and characterized. Deposition temperature for oxidation layer was $1100^{\circ}C$~130$0^{\circ}C$ by $O_2$ and Ar atmosphere. The oxide thickness, surface morphology, and interface characteristic of deposited oxide layers were measurement by ellipsometer, SEM, TEM, AFM, and SIMS. Thickness of oxidation layer was confirmed 50nm and 90nm to with deposition temperature at $1150^{\circ}C$ and $1200{\circ}C$ for dry 4 hours and wet 1 hour, respectively. For the high purity oxidation layer, the necessity of sacrificial oxidation which is etched for the removal of the defeats on the wafer after quickly thermal oxidation was confirmed.

A Study on the Electrical Properties of $Ta_2O_{5}$ Thin Films by Atomic Layer Deposition Method in MOS Structure (MOS구조에서의 원자층 증착 방법에 의한 $Ta_2O_{5}$ 박막의 전기적 특성에 관한 연구)

  • 이형석;장진민;임장권;하만효;김양수;송정면;문병무
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.52 no.4
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    • pp.159-163
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    • 2003
  • ln this work, we studied electrical characteristics and leakage current mechanism of $Ta_2O_{5}$ MOS(Metal-Oxide-Semiconductor) devices. $Ta_2O_{5}$ thin film (63 nm) was deposited by ALD(Atomic Layer Deposition) method at temperature of 235 $^{\circ}C$. The structures of the $Ta_2O_{5}$ thin films were examined by XRD(X-Ray Diffraction). From XRD, it is found that the structure of $Ta_2O_{5}$ is single phase and orthorhombic. From capacitance-voltage (C-V) anaysis, the dielectric constant was 19.4. The temperature dependence of current density-electric field (J-E) characteristics of $Ta_2O_{5}$ thin film was studied at temperature range of 300 - 423 K. In ohmic region (<0.5 MV/cm), the resistivity was 2.456${\times}10^{14}$ ($\omega{\cdot}cm$ at 348 K. The Schottky emission is dominant at lower temperature range from 300 to 323 K and Poole-Frenkel emission is dominant at higher temperature range from 348 to 423 K.

The RF performance degradation in Bulk DTMOS due to Hot Carrier effect (Hot Carrier 현상에 의한 Bulk DTMOS의 RF성능 저하)

  • Park Jang-Woo;Lee Byoung-Jin;Yu Jong-Gun;Park Jong-Tae
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.2 s.332
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    • pp.9-14
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    • 2005
  • This paper reports the hot carrier induced RF performance degradation of bulk dynamic threshold voltage MOSFET (B-DTMOS) compared with bulk MOSFET (B-MOS). In the normal and moderate mode operations, the degradations of cut-off frequency $(f_{T})$ and minimum noise figure $(F_{min})$ of B-DTMOS are less significant than those of B-MOS devices. Our experimental results show that the RF performance degradation is more significant than the U performance degradation after hot carrier stressing. Also, the degradation characteristics of RF power Performance of B-DTMOS due to hot carrier effects are measured for the first time.

INTEGRATED MAGNETIC SENSORS: AN OVER VIEW

  • Cristolovenau, Sorin
    • The Magazine of the IEIE
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    • v.13 no.1
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    • pp.86-95
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    • 1986
  • The basic physical principles involved in the operation of monolithic magnetic sensors are reviewed and technological aspects outlined. More or less conventional devices based on Hall effect, magnetoresistance or current path deflection are described. It is shown that such sensors with 2, 3, 4 or 5 terminal contacts are achievable with standard silicon integrated circuit process. Several kinds of magnetodiodes (p+nn+,p+n, Schottky, MOS, memory, CMOS) have been fabricated on Si and on SOS films and present attractive properties. Finally, the magneto-transistor family is discussed with emphasis to split-terminals, CMOS, unijunction and fila-mentary devices.

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Characteristics of Metal-Oxide- Semiconductor (MOS) Devices with Tungsten Silicide for Alternate Gate Metal (텅스텐 실리사이드를 차세대 게이트 전극으로 이용한 MOS 소자의 특성 분석)

  • No, Gwan-Jong;Yun, Seon-Pil;Yang, Seong-U;No, Yong-Han
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.7
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    • pp.513-519
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    • 2001
  • We proposed Si-rich tungsten silicide (WSix) films for alternate gate electrode of deep-submicron MOSFETs. The investigation of WSix films deposited directly on SiO$_2$ indicated that the annealing of as-deposited films using a rapid thermal processor (RTP) results in low resitivity, as well as negligible fluorine (F) diffusion. Specifically, the resitivity of RTP-annealed samples at 800 $^{\circ}C$ for 3 minutes in vacuum was ~160 $\mu$$\Omega$ . cm, and the irregular growth of an extra SiO$_2$ layer due to F diffusion during annealing has not been observed. In addition, the analysis of the WSix-SiO$_2$-Si (MOS) capacitors exhibits excellent electrical characteristics.

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Design of a Gate-VDD Drain-Extended PMOS ESD Power Clamp for Smart Power ICs (Smart Power IC를 위한 Gate-VDD Drain-Extened PMOS ESD 보호회로 설계)

  • Park, Jae-Young;Kim, Dong-Jun;Park, Sang-Gyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.10
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    • pp.1-6
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    • 2008
  • The holding voltage of the high-voltage MOSFETs in snapback condition is much smaller than the power supply voltage. Such characteristics may cause the latcup-like problems in the Smart Power ICs if these devices are directly used in the ESD (Electrostatic Discharge) power clamp. In this work, a latchup-free design based on the Drain-Extended PMOS (DEPMOS) adopting gate VDD structure is proposed. The operation region of the proposed gate-VDD DEPMOS ESD power clamp is below the onset of the snapback to avoid the danger of latch-up. From the measurement on the devices fabricated using a $0.35\;{\mu}m$ BCD (Bipolar-CMOS-DMOS) Process (60V), it was observed that the proposed ESD power clamp can provide 500% higher ESD robustness per silicon area as compared to the conventional clamps with gate-driven LDMOS (lateral double-diffused MOS).

Temperature Dependence of DC and RF characteristics of CMOS Devices (RF-CMOS소자의 온도에 따른 DC및 RF 특성)

  • Nam, Sang-Min;Lee, Byeong-Jin;Hong, Seong-Hui;Yu, Jong-Geun;Jeon, Seok-Hui;Gang, Hyeon-Gyu;Park, Jong-Tae
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.3
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    • pp.20-26
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    • 2000
  • In this work, the degradation of g$_{m}$ , f$_{T}$ and f$_{max}$ of RF-CMOS devices have been characterized at elevated temperature. Since MOS transistors in RF applications are usually in saturation region, a simple empirical model for temperature dependence of g$_{m}$ at any measurement bias has been suggested. Because f$_{T}$ and f$_{max}$ of CMOS devices are proportional to g$_{m}$, the temperature dependence of f$_{T}$ and f$_{max}$ could be obtained from the temperature dependence of g$_{m}$. It was found that the degradation of f$_{T}$ and f$_{max}$ at elevated temperature was due to the degradation of g$_{m}$. From the correlation between DC and RF performances of CMOS devices, we can predict the enhanced f$_{T}$ and f$_{max}$ performances at low temperature.

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Process Characteristics of Thin Dielectric at MOS Structure (MOS 구조에서 얇은 유전막의 공정 특성)

  • Eom, Gum-Yong;Oh, Hwan-Sool
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.11a
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    • pp.207-209
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    • 2004
  • Currently, for satisfying the needs of scaled MOSFET's a high quality thin oxide dielectric is desired because the properties of conventional $SiO_2$ film are not acceptable for these very small sized transistors. As an alternative gate dielectric have drawn considerable alternation due to their superior performance and reliability properties over conventional $SiO_2$, to obtain the superior characteristics of ultra thin dielectric films, $N_2O$ grown thin oxynitride has been proposed as a dielectric growtuanneal ambient. In this study the authors observed process characteristics of $N_2O$ grown thin dielectric. In view points of the process characteristics of MOS capacitor, the sheet resistance of 4.07$[\Omega/sq.]$, the film stress of $1.009e^{10}[dyne/cm^2]$, the threshold voltage$(V_t)$ of 0.39[V], the breakdown voltage(BV[V]) of 11.45[V] was measured in PMOS. I could achieve improved electrical characteristics and reliability for deep submicron MOSFET devices with $N_2O$ thin oxide.

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Optimal Design of Field Ring for Power Devices (고 내압 전력 소자 설계를 위한 필드 링 최적화에 관한 연구)

  • Kang, Ey-Goo
    • Journal of IKEEE
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    • v.14 no.3
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    • pp.199-204
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    • 2010
  • In this paper, we proposed trench field ring for breakdown voltage of power devices. The proposed trench field ring was improved 10% efficiency comparing with conventional field ring. we analyzed five parameters of trench field ring for design of trench field ring and carried out 2-D devices simulation and process simulations. That is, we analyzed number of field ring, juction depth, distance of field rings, trench width, doping profield. The proposed trench field ring was better to more 1000V.