• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2013년도 춘계학술대회
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• pp.789-790
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• 2013

기존 MOS (Metal-Oxide-Semiconductor) 소자의 게이트 산화막으로 사용된 $Er_2O_3/SiO_2$ 더블레이어 층은 낮은 누설전류와 높은 캐패시턴스를 갖는 장점을 가지고 있다. 본 논문에서는 이 더블레이어 층을 비휘발성 메모리 소자의 전하포획층으로 처음 적용하여 우수한 성능의 메모리 특성을 얻을 수 있었다. 소자를 제작하기 전에 EDISON Nanophysics 시뮬레이션을 통해 낮은 누설 전류값과 높은 캐패시턴스 값을 기준으로 하여 산화막 두께를 최적화하였다. 이 후, 최적화된 조건으로 금속실리사이드 소스/드레인, 10 um/ 10um의 채널 넓이/길이를 갖는 비휘발성 메모리 소자를 제작하였다. 그 결과, 11 V, 50 ms의 프로그램 특성, -11 V, 500 ms의 소거 특성 및 10년의 기억유지 특성, $10^4$의 내구성 특성을 얻을 수 있었다.

• Transactions on Electrical and Electronic Materials
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• 제5권5호
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• pp.169-172
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• 2004

Deep sub-micron device required to get the superior ultra thin gate oxide characteristics. In this research, I will recommend a novel shallow trench isolation structure(STI) for thin gate oxide and a $N_2$O gate oxide 30 $\AA$ by NO ambient process. The local oxidation of silicon(LOCOS) isolation has been replaced by the shallow trench isolation which has less encroachment into the active device area. Also for $N_2$O gate oxide 30 $\AA$, ultra thin gate oxide 30 $\AA$ was formed by using the $N_2$O gate oxide formation method on STI structure and LOCOS structure. For the metal electrode and junction, TiSi$_2$ process was performed by RTP annealing at 850 $^{\circ}C$ for 29 sec. In the viewpoints of the physical characteristics of MOS capacitor, STI structure was confirmed by SEM. STI structure was expected to minimize the oxide loss at the channel edge. Also, STI structure is considered to decrease the threshold voltage, result in a lower Ti/TiN resistance( Ω /cont.) and higher capacitance-gate voltage(C- V) that made the STI structure more effective. In terms of the TDDB(sec) characteristics, the STI structure showed the stable value of 25 % ～ 90 % more than 55 sec. In brief, analysis of the ultra thin gate oxide 30 $\AA$ proved that STI isolation structure and salicidation process presented in this study. I could achieve improved electrical characteristics and reliability for deep submicron devices with 30 $\AA$ $N_2$O gate oxide.

• Transactions on Electrical and Electronic Materials
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• 제14권5호
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• pp.235-241
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• 2013

A low power CMOS control circuit is applied in an integrated DC-DC buck converter. The integrated converter is composed of a feedback control circuit and power block with 0.35 ${\mu}m$ CMOS process. A current-sensing circuit is integrated with the sense-FET method in the control circuit. In the current-sensing circuit, a current-mirror is used for a voltage follower in order to reduce power consumption with a smaller chip-size. The N-channel MOS acts as a switching device in the current-sensing circuit where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time. The converter offers well-controlled output and accurately sensed inductor current. Simulation work shows that the current-sensing circuit is operated with an accuracy of higher than 90% and the transient time of the error amplifier is controlled within $75{\mu}sec$. The sensing current is in the range of a few hundred ${\mu}A$ at a frequency of 0.6~2 MHz and an input voltage of 3~5 V. The output voltage is obtained as expected with the ripple ratio within 1%.

• 대한전자공학회논문지
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• 제25권11호
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• pp.1286-1293
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• 1988

자기정렬 DMOS 트랜지스터의 채널 길이에 관한 수식을 2차원적인 Caussian 농도분포식으로부터 유도하였다. 본 논문에서는 제시된 채널 길이에 관한 수식은 기판의 농도, 이중확산된 각 영역의 표면 농도와 수직 접합 깊이의 함수로 이루어져 있으며, 계산된 실험치와 잘 일치하고 있다. 또한 고전압용 DMOS 트랜지스터에서 채널 punchthrough를 억제할 수 있는 최소 채널 길이를 채널영역의 평균농도를 이용하여 계산하였으며 소자 simulation을 통하여 최적의 채널 조건(채널농도분포 및 채널 길이)를 예측할 수 있음을 확인하였다.

• 대한전자공학회논문지
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• 제26권11호
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• pp.1666-1671
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• 1989

A novel switched-capacitor circuit for interfacing capacitive microtransducers with a digital system is developed based on the dual-slope integration. It consists of a differential integrator and a comparator. Driven by the teo phase clock, the circuit first senses the capacitance difference between the transducer and the reference capacitor in the form of charge, and accumulates it into the feedback capabitor of the integrator for a fixed period of time. The resulant accumulated charge is next extracted by the known reference charge until the integrator output voltage refurns to zero. The length of time required for the integrator output to return to zero, as measured by the number of clock cycle gated into a counter is proportional to the capacitance difference, averaged over the integration period. The whole operation is insensitive to the reference voltage and the capacitor values involved in the circuit, Thus the proposed circuit permits an accurate differental capacitance measurement. An error analysis has showh that the resolution as high as 8 bits can be expected by realizing the circuit in a monolithic MOS IC form. Besides the accuracy, it features the small device count integrable onto a small chip area. The circuit is thus particularly suitadble for the on-chip interface.

• 센서학회지
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• 제17권1호
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• pp.41-52
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• 2008

In this paper, a circuit analysis of the complementary CMOS active pixel and readout circuit is carried out. Complementary pixel structure which is different from conventional 3TR APS structure is consist of photo diode, reset PMOS, several NMOSs and PMOSs sets for complementary signals. Photo diode is modelled with Medici device program. HSPICE was used to analyze the variation of the signal feature depending on light intensity using $0.5{\mu}M$ standard CMOS process. Simulation results show that the output signal range is from 0.8 V to 4.5 V. This signal range increased 135 % output dynamic range compared to conventional 3TR pixel in the condition of 5 V power supply.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.223-226
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• 2003

We propose an improvement method for a $\underline{G}ate$ $\underline{OX}ide(GOX)$ thinning at the edge of $\underline{S}hallow$ $\underline{T}rench$ $\underline{I}solation(STI)$, when STI is adopted to Dual Gate Oxide(DGOX) Process. In the case of SOC(System On-a-Chip), the DGOX process is usually used for realizing both a low and a high voltage parts in one chip. However, it is found that the severe GOX thinning occurs from at STI top edge region and a dent profile exists at the top edge of STI, when conventional DGOX and STI process carried out in high density device chip. In order to overcome this problem, a new DGOX process is tried in this study. And we are able to prevent the GOX thinning by H2 anneal, partially SiN liner skip, and a method which is merged a thick sidewall oxide(S/O) with a SiN pull-back process. Therefore, a good subthreshold characteristics without a double hump is obtained by the prevention of a GOX thinning and a deep dent profile.

• 대한전자공학회논문지
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• 제21권5호
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• pp.67-78
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• 1984

프로팅 게이트 위에 컨트롤 게이트를 갖는 n-채널 이중 다결정 실리콘게이트 EAROM을 제작하였다. 채널 길이는 4-8μm, 채널 폭은 5-14μm로 하여 5μm design rule에 따라 설계하였으며 서로 다른 4가지 컨트롤게이트 구조를 갖는 채널 주입형 기억소자를 얻었다. 그리고 소자의 Punch through 전압과 게이트에 의해 조절되는 채널파괴 전압을 증가시키기 위해 이중 이온주입 (double ion implantation)과 active 영역에 보론이온을 주입 하였다. 프로그래밍을 위해 드레인 전압 및 게이트 전압이 각각 13-l7V 및 20-25V 정도 필요하였다. 그리고 제조된 기억소자의 소거는 광학적 방법뿐 아니라 전기적 방법으로도 가능하였으며 125℃에서 200시간 유지하였을 때 축적된 전자가 약 4 %정도 감소함을 알 수 있었다.

• 센서학회지
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• 제24권5호
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• pp.353-357
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• 2015

A new SPICE-compatible model for a gate/body-tied PMOSFET photodetector (GBT PD) with an overlapping control gate is presented. The proposed SPICE-compatible model of a GBT PD with an overlapping control gate makes it possible to control the photocurrent. Research into GBT PD modeling was proposed previously. However, the analysis and simulation of GBT PDs is not lacking. This SPICE model concurs with the measurement results, and it is simpler than previous models. The general GBT PD model is a hybrid device composed of a MOSFET, a lateral bipolar junction transistor (BJT), and a vertical BJT. Conventional SPICE models are based on complete depletion approximation, which is more applicable to reverse-biased p-n junctions; therefore, they are not appropriate for simulating circuits that are implemented with a GBT PD with an overlapping control gate. The GBT PD with an overlapping control gate can control the sensitivity of the photodetector. The proposed sensor is fabricated using a $0.35{\mu}m$ two-poly, four-metal standard complementary MOS (CMOS) process, and its characteristics are evaluated.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.240-240
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• 2010

A multiple alloy metal nano-dots memory using FN tunneling was investigated in order to confirm its structural possibility for future flash memory. In this work, a multiple FePt nano-dots device with a high work function (~5.2 eV) and extremely high dot density (${\sim}\;1.2{\times}10^{13}/cm^2$) was fabricated. Its structural effect for multiple layers was evaluated and compared to one with a single layer in terms of the cell characteristics and reliability. We confirm that MOS capacitor structures with 2-4 multiple FePt nano-dot layers provide a larger threshold voltage window and better retention characteristics. Furthermore, it was also revealed that several process parameters for block oxide and inter-tunnel oxide between the nano-dot layers are very important to improve the efficiency of electron injection into multiple nano-dots. From these results, it is expected that a multiple FePt nano-dots memory using Fowler-Nordheim (FN)-tunneling could be a candidate structure for future flash memory.