• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.8
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• pp.38-43
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• 1998

An analytical model for the surface field distribution of the RESURF (reduced surface field)LD(lateral double-diffused) MOS is presented in terms of the doping concentration, the thickness of the n epi layer, the p substrate concentration, and the epi layer length. The reuslts are used to determine the breakdown voltage due to the surface field as a function of the epi layer length. The maximum breakdown voltage of the device is found to be that of the vertical n$^{+}$n$^{[-10]}$ p$^{[-10]}$ junction. Analytical results of the breakdown voltage vs. the epi layer length agree well with the numerical simulation results using MEDICI.I.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.1
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• pp.77-83
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• 1994

Characteristics of hot-electron-induced degradation by AC, DC was investigated for p-MOSFET's(W/L=25/l$\mu$m) with sub-10nm RTP-CVD gate oxides. It was confirmed that the surface channel p-MOSFET of a thinner gate oxide shows less degradation. Mechanisms for this effect were analyzed using a simple MOS Device degradation model. It was found that the number of generated electron traps(fixed charge) is determined by the amount of peak gate current, dependent of the gate oxide thickness, and the major cause of the smaller degradation in the thinner gate oxide devices is the lower hot electron trapping carriers.

• Journal of information and communication convergence engineering
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• v.13 no.3
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• pp.189-196
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• 2015

In this paper, we present a rotating auto-zeroing offset cancellation technique, which can improve the performance of touch screen sensing circuits. Our target touch screen detection method employs multiple continuous sine waves to achieve a high speed for large touch screens. While conventional auto-zeroing schemes cannot handle such continuous signals properly, the proposed scheme does not suffer from switching noise and provides effective offset cancellation for continuous signals. Experimental results show that the proposed technique improves the signal-to-noise ratio by 14 dB compared to a conventional offset cancellation scheme. For the realistic simulation results, we used Cadence SPECTRE with an accurate TSP model and noise source. We also applied an asymmetric device size (10% MOS size mismatch) to the OP Amp design in order to measure the effectiveness of offset cancellation. We implemented the proposed circuit as part of a touch screen controller system-on-chip by using a Magnachip/SK Hynix 0.18-µm complementary metal-oxide semiconductor (CMOS) process.

• Journal of information and communication convergence engineering
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• v.16 no.1
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• pp.60-65
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• 2018

The Internet of Things (IoT) is happening now. By implementing IoT, we can build smart home system. Smart home is an application that is a combination of technology and services that specialize in the home environment with specific functions aimed at improving the efficiency, comfort and security of the occupants. Smart homes filled with connected products are loaded with possibilities to make our lives easier, more convenient, and more comfortable. This intelligent home system uses a microcontroller to process functions that provided by smart home system, such functions as RFID for door access and PIR sensors for motion detection. By using Android users could control the sensors anytime and anywhere. Microcontroller used is Arduino IDE with WeMos D1R2 board. Based on the testing process, there was a successful communication between the components of the device, sensors, and Android devices. Users could open or close the solenoid, users can also turn off or turn on electronic devices using Android.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.36 no.7
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• pp.462-469
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• 1987

A metal gate MOSFET with source/drain regions self-aligned to gate region is proposed. The proposed MOS transistor is fabricated by utilizing the higher oxidation rate of source/drain regions with high doping concentration when compared with channel region with moderate doping. The thick oxide on the source/drain regions reduces the gate and drain(source) overlap capacitance down to that of a self-aligned polysilicon gate device while allowing the use of a metal gate with much lower resistivity than the more commonly used polycrystalline silicon. A ring oscillator composed of 15 inverter stages has been computer simulated using SPICE. The results of the simulation show good agreement with experimental measurement confirming the fast switching speed of propesed MOSFET.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.359-359
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• 2010

IGBT(Insulated Gate Bipolar Transistor) 란 MOS(Metal Oxide Silicon) 와 Bipolar 기술의 결정체로 낮은 순방향 손실(Low Saturation)과 빠른 Speed를 특징으로 기존의 Thyristor, BJT, MOSFET 등으로 실현 불가능한 분양의 응용처를 대상으로 적용이 확대 되고 있고, 300V 이상의 High Power Application 영역에서 널리 사용되고 있는 고효율, 고속의 전력 시스템에 있어서 필수적으로 이용되는 Power Device이다. IGBT는 출력 특성 면에서 Bipolar Transistor 이상의 전류 능력을 가지고 있고 입력 특성 면에서 MOSFET과 같이 Gate 구동 특성을 갖기 때문에 High Switching, High Power에 적용이 가능한 소자이다. 반면에, Conventional IGBT는 MOSFET과 달리 IGBT 내부에 Anti-Parallel Diode가 없기 때문에 Inductive Load Application 적용시에는 별도의 Free Wheeling Diode가 필요하다. 그래서, 본 논문에서 별도의 Anti-Parallel Diode의 추가 없이도 Inductive Load Application에 적용 가능한 RC IGBT를 적용하여 600V/15A급 Three Phase Inverter Module을 제안 하고자 한다.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.197-197
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• 1999

Gate oxide 의 두께 감소는 gate의 캐패시턴스를 증가시켜 트랜지스터의 속도를 빠르게 하며, 동시에 저전압 동작을 가능하게 하기 때문에 gate oxide 두께는 MOS 공정 세대가 진행되어감에 따라 계속 감소할 것이다. 이러한 얇은 산화막은 device design에 명시된 두께의 특성을 나타내야 한다. Gate oxide의 두께가 작아질수록 gate oxide와 crystalline silicon간의 계면효과가 박막의 두께의 결정에 심각한 영향을 주기 때문에 정확한 두께 계측이 어렵다. 이러한 영향과 계측방법에 따라서 두께 계측의 차이가 나타난다. XTEM은 사용한 parameter에, Ellipsometer는 refractive index에, MEIS(Medium) Energy Ion Scattering)은 에너지 분해능에, Capacitor-Voltage 측정은 depletion effect에 의해 영향을 받는다. 우리는 계면의 원자분해능 분석에 통상 사용되어온 High Resolution TEM을 이용하여 약 30~70$\AA$ SiO2층의 두께와 계면 구조에 대한 분석을 하여 이를 MEIS와 0.015nm의 고감도를 가진 SE(Spectroscopy Ellipsometer), C-V 측정 결과와 비교하여 가장 좋은 두께 계측 방법을 찾고자 한다.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2008.04a
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• pp.247-250
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• 2008

최근 무선통신용 LSI는 배터리 수명과 관련하여, 저전력 동작이 중요시되고 있다. 따라서 Digital CMOS 신호처리와 더불어 동작 가능한 SI (Switched-Current) circuit를 이용하는 Current-mode 신호처리가 주목받고 있다. 그러나 SI circuit의 기본인 Current Memory는 Charge Injection에 의한 Clock Feedthrough라는 문제점을 갖고 있기 때문에, 전류 전달에 있어서 오차를 발생시킨다. 본 논문에서는 Current Memory의 문제점인 Clock Feedthrough의 해결방안으로 CMOS Switch의 연결을 검토하였고, 0.25${\mu}m$ CMOS process에서 Memory MOS와 CMOS Switch의 Width의 관계는 simulation 결과를 통하여 확인하였으며, MOS transistor의 관계를 분명히 하여, 설게의 지침을 제공한다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.6
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• pp.43-49
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• 1997

Tungsten poycide has studied gate oxide reliability and dielectric strength charactristics as the composition of gate electrode which applied submicron on CMOS and MOS device for optimizing gate electrode resistivity. The gate oxide reliability has been tested using the TDDB(time dependent dielectric breakdwon) and SCTDDB (stepped current TDDB) and corelation between polysilicon and WSi$_{2}$ layer. iN the case of high intrinsic reliability and good breakdown chracteristics on polysilicon, confirmed that tungsten polycide layer is a better reliabilify properities than polysilicon layer. Also, hole trap is detected on the polysilicon structure meanwhile electron trap is detected on polycide structure. In the case of electron trap, the WSi$_{2}$ layer is larger interface trap genration than polysilicon on large POCL$_{3}$ doping time and high POCL$_{3}$ doping temperature condition. WSi$_{2}$ layer's leakage current is less than 1 order and dielectric strength is a larger than 2MV/cm.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.1
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• pp.1-6
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• 2002

The hot carried degradation in a metal oxide semiconductor device has been one of the most serious concerns for MOS-ULSI. In this paper, three types of LDD(lightly doped drain) structure for suppression of hot carried degradation, such as decreasing of performance due to spacer-induced degradation and increase of series resistance will be investigated. in this study, LDD-nMOSFETs used had three different drain structure, (1) conventional surface type LDD(SL), (2) Buried type LDD(BL), (3) Surface implantation type LDD(SI). As experimental results, the surface implantation the LDD structure showed that improved hot carrier lifetime to comparison with conventional surface and buried type LDD structures.