• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.7
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• pp.963-968
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• 2013

Ionizing Radiation effects on MOS devices provide useful information regarding the behavior of MOS based devices and circuits in the electronic instrumentation parts and instructive data for making the high sensitive sensors. The study presents the results of the analysis on the structural characteristics of MOS capacitor for sensing the ionizing radiation effect. We performed numerical modeling of Ionizing-radiation effect on MOS capacitor and simulation using Matlab program. Also we produced MOS capacitors and obtained useful data through radiation experiment to analyse the characteristic of ionizing radiation effect on MOS capacitor. Increasing the thickness of MOS capacitor's oxide layer enhanced the sensitivity of MOS capacitor under irradiation condition, but the sensitivity of irradiated MOS capacitor is uninfluenced by the area of MOS capacitor. The high frequency capacitance of the MOS capacitor is found to be strongly affected by incident ionizing radiation.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1181-1182
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• 2008

The study presents the results of the analysis on the structural characteristics of MOS capacitor for sensing the ionizing radiation effect. Increasing the thickness of MOS capacitor's oxide layer enhanced the sensitivity of MOS capacitor under irradiation condition, but the sensitivity of irradiated MOS capacitor is uninfluenced by the area of MOS capacitor.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.2
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• pp.126-129
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• 2006

We investigated an optimized condition of the capacitor threshold voltage implantation(capacitor $V_T$ Implant) in planar P-MOS DRAM Cell. Several samples with different condition of the capacitor $V_T$ Implant were prepared. It appeared that for the capacitor $V_T$ Implant of $BF_2\;2.0{\times}l0^{13}\;cm^{-2}$ 15 KeV, refresh time is three times larger than that of the sample, in which capacitor $V_T$ Implant is in $BF_2\;1.0{\times}l0^{13}\;cm^{-2}$ 15 KeV. Raphael simulation revealed that the lowed maximum electric field and lowed minimum depletion capacitance ($C_{MIN}$) under the capacitor resulted in well refresh characteristics.

• Journal of the Semiconductor & Display Technology
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• v.9 no.3
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• pp.75-78
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• 2010

In this study we investigated the electrical properties of ZnO-based MOS capacitor with $HfO_2$ as the gate dielectric. MIM capacitor, which uses either $HfO_2$ or $Al_2O_3$ as the dielectric layer, is also studied to understand the dependency of the dielectrics on the preparation conditions. It was found that thinner $HfO_2$ films yield better electrical properties, namely lower leakage current and higher breakdown electric field. These properties were observed to deteriorate when subsequently annealed. Capacitance in the depletion region of MOS capacitor was found to increase with UV ozone treatment time up to 60min. However, when the treatment time was extended to 120min, the trend is reversed. The 'threshold voltage' was also observed to positively shift with UV ozone treatment time up to 60min. The shift apparently saturated for longer treatment.

• Journal of IKEEE
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• v.18 no.4
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• pp.447-455
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• 2014

In this research, n-based 4H-MOS Capacitor was fabricated with PECVD (plasma enhanced chemical vapor deposition) process for improving SiC/$SiO_2$ interface properties known as main problem of 4H-SiC MOSFET. To overcome the problems of dry oxidation process such as lower growth rate, high interface trap density and low critical electric field of $SiO_2$, PECVD and NO annealing processes are used to MOS Capacitor fabrication. After fabrication, MOS Capacitor's interface properties were measured and evaluated by hi-lo C-V measure, I-V measure and SIMS. As a result of comparing the interface properties with the dry oxidation case, improved interface and oxide properties such as 20% reduced flatband voltage shift, 25% reduced effective oxide charge density, increased oxide breakdown field of 8MV/cm and best effective barrier height of 1.57eV, 69.05% reduced interface trap density in the range of 0.375~0.495eV under the conduction band are observed.

• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.362-364
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• 2016

본 논문에서는 MOS(Metal Oxide Semiconductor) Capacitor의 산화막내에 다양한 원인에 의해 존재하는 비이상적인 전하들 중 Fixed Oxide Charge가 소자의 문턱전압에 어떤 영향을 주는지 분석했다. 분석한 결과 n+ polysilicon Gate를 가지고, 산화막인 $SiO_2$의 두께가 3nm이고, 도핑농도가 $10^{18}cm^{-2}$인 P형 실리콘 기판으로 이루어진 MOS Capacitor에서 Fixed Oxide Charge Density가 $C/cm^2$ 이상일 때 문턱전압을 0.01V 이상 감소시키고 $C/cm^2$ 이하일 때 문턱전압을 0.01V 이상 증가시켰다.

• Proceedings of the KIEE Conference
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• 1984.07a
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• pp.197-198
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• 1984

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.11a
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• pp.123-127
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• 1992

When MOS devices is exposed to radiation, radiation effects of P-type MOS capacitor can cause modulation and/or degradation in devices characteristics and its operating life. The oxide layer is grown in $O_2$+T.C.E. and its thickness ranges from 40 to 80 nm. Irradiations on MOS capacitor were performed by Cobalt-60 gamma ray source and total dose ranges from $10^4$ to $10^8$ rads. The radiation effect on electrical conduction characteristics(I-V) in MOS capacitor was measured as a function of gate oxide thickness and total dose. From the experimental result, I-V characteristics is found to be influenced strongly by total dose in irradiated p-type MOS capacitors. The ohmic current is dependant on of total dose in irradiated P-type MOS capacitors. This results are explained using surface states at interface radiation-induced traps.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.6
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• pp.2697-2701
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• 2012

The yield of OTP devices using anti-fuse MOS capacitor have been affected by the input resistance, the size of the pass transistor and the read transistor, and the readout voltage of programed cell. To investigate the element which gives an effect to yield, we analyze the full map data of the resistance characterization of OTP device and those data in a various experimental condition. As a result, we got the optimum conditions which is necessary to the yield improvement. The optimum conditions are as follows: Input resistance is 50 ohms, the channel length of pass transistor is 10um, read voltage is 2.8 volt, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.9-10
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• 2007

In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition(ALD). And we studied the electrical characterization of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3\;at\;350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. The MOS capacitor of round-type was fabricated on Si substrates. Through TEM(Transmission Electron Microscope), XRD(X-ray Diffraction), capacitance-voltage(C-V) and current-voltage(I-V) analysis, the role of thin Hf metal layer for the better $HfO_2$/Si interface property was investigated.