• 제목/요약/키워드: MOS

검색결과 1,181건 처리시간 0.041초

MOS 제어 다이리스터의 특성 해석 및 시뮬레이션을 위한 모델 (Switching Characteristics and PSPICE Modeling for MOS Controlled Thyristor)

  • 이영국;현동석
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1994년도 하계학술대회 논문집 A
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    • pp.237-239
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    • 1994
  • The MOS-controlled thyristor(MCT) is a new power semi-conductor device that combines four layers thyristor structure presenting regenerative action and MOS-gate providing controlled turn-on and turn-off. The MCT has very fast switching speed owing to voltage controlled MOS-gate, and very low on-state voltage drop resulting from regenerative action of four layers thyristor structure. In addition, because of a higher dv/dt rating and di/dt rating, gate drive circuit and snubber circuit can be simpler comparing to other power switching devices. So recently much interest and endeavor is being applied to develop the performance and ratings of the MCT. This paper describes the switching characteristic of the MCT for its practical applications and presents a model for PSPICE circuit simulation. The model for PSPICE circuit simulation is compared to the experimental result using MCTV75P60F1 made by Harris co..

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증착시 도핑된 비정질 Si 게이트를 갖는 MOS 캐패시터와 트랜지스터의 전기적 특성 (Electrical Properties of MOS Capacitors and Transistors with in-situ doped Amorphous Si Gate)

  • 이상돈;이현창;김재성;김봉렬
    • 전자공학회논문지A
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    • 제31A권6호
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    • pp.107-116
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    • 1994
  • In this paper, The electrical properties of MOS capacitors and transistoras with gate of in-situ doped amorphous Si and poly Si doped by POCI$_3$. Under constant current F-N stress, MOS capacitors with in-situ doped amorphous Si gate have shown the best resistance to degradation in reliabilty properties such as increase of leakage current, shift of gate voltage (V$_{g}$). shift of flat band voltage (V$_{fb}$) and charge to breakdown(Q$_{bd}$). Also, MOSFETs with in-situ doped amorphous Si gate have shown to have less degradation in transistor properties such as threshold voltage, transconductance and drain current. These improvements observed in MOS devices with in-situ doped amorphous Si gate is attributed to less local thinning spots at the gate/SiO$_2$ interface, caused by the large grain size and the smoothness of the surface at the gate/SiO$_2$ interface.

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70 nm nMOS의 RF 적용을 위한 transistor matching (Transistor Matching in 70 nm nMOS for RF applications)

  • 최현식;홍승호;정윤하
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2006년도 하계종합학술대회
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    • pp.583-584
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    • 2006
  • This paper presents transistor matching in 70 nm nMOS. To adopt radio frequency(RF) applications, the RF performance, especially the current gain cutoff frequency($f_T$), is examined experimentally through a wafer. It is proved that the RF performance variation of 70 nm nMOS is dependent to the device geometry, the total width(W). The RF performance variation of 70 nm nMOS is inversely proportional to square root of total width(W). Also, decreasing of the number of fingers($N_f$) is helpful to decrease the variation of 70 nm nMOS.

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Buried Channel MOS 구조를 이용한 표면생성속도 측정 방법 (A Surface Generation Velocity Measurement Technique Using the Buried Channel MOS Structure)

  • 조성호;허연철;이종덕
    • 전자공학회논문지A
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    • 제29A권7호
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    • pp.56-63
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    • 1992
  • A measurement technique of the surface generation velocity S$_o$ using the BC(buried channel) MOS structure with shallow and low doped channel layer (BC MOS S$_o$ measurement technique) is presented and verified analytically and experimentally. Using this measurement technique, S$_o$ can be measured more accurately than that measured using the gate-controlled diode SS1oT measurement technique. When S$_o$ is measured for the two techniques from a BC MOS structure test patten with gate length of 171$\mu$m, the results are 0,66cm/sec and 0.28cm/sec for the former and the latter respectively.

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고유전체 박막에 형성된 Ge 나노크리스탈을 이용한 MOS 커패시터의 전기적 특성 (Electrical characteristics of MOS capacitors with Ge nanocrystals embedded in high-k materials)

  • 윤정권;이혜령;박병준;조경아;김상식
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2007년도 제38회 하계학술대회
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    • pp.1351-1352
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    • 2007
  • $ZrO_2$$HfO_2$ 박막에 이온 주입을 거친 후 열처리 과정을 통해 Ge 나노입자를 형성시켜 MOS 커패시터를 제작하였다. C-V 곡선에서는 반시계 방향의 hysteresis가 관찰되었으며, $ZrO_2$ MOS 커패시터에서는 -9 V에서 9 V까지 전압변화를 주었을 때 3 V 정도의 메모리 윈도우가 나타남을 확인 할 수 있었다. 또한, $HfO_2$ MOS 커패시터에서는 -10 V에서 10 V까지 전압변화를 주었을 때 3.45 V의 메모리 윈도우를 관찰 할 수 있었다.

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ZnO를 사용한 MOS 커패시터의 제작 조건에 따른 특성 변화 (Property Variations of ZnO-based MOS Capacitor with Preparation Conditions)

  • 남형진
    • 반도체디스플레이기술학회지
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    • 제9권3호
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    • pp.75-78
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    • 2010
  • In this study we investigated the electrical properties of ZnO-based MOS capacitor with $HfO_2$ as the gate dielectric. MIM capacitor, which uses either $HfO_2$ or $Al_2O_3$ as the dielectric layer, is also studied to understand the dependency of the dielectrics on the preparation conditions. It was found that thinner $HfO_2$ films yield better electrical properties, namely lower leakage current and higher breakdown electric field. These properties were observed to deteriorate when subsequently annealed. Capacitance in the depletion region of MOS capacitor was found to increase with UV ozone treatment time up to 60min. However, when the treatment time was extended to 120min, the trend is reversed. The 'threshold voltage' was also observed to positively shift with UV ozone treatment time up to 60min. The shift apparently saturated for longer treatment.

DC voltage control by drive signal pulse-width control of full-bridged inverter

  • Ishikawa, Junichi;Suzuki, Taiju;Ikeda, Hiroaki;Mizutani, Yoko;Yoshida, Hirofumi
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1996년도 Proceedings of the Korea Automatic Control Conference, 11th (KACC); Pohang, Korea; 24-26 Oct. 1996
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    • pp.255-258
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    • 1996
  • This paper describes a DC voltage controller for the DC power supply which is constructed using the full-bridged MOS-FET DC-to-RF power inverter and rectifier. The full-bridged MOS-FET DC-to-RF inverter consisting of four MOSFET arrays and an output power transformer has a control function which is able to control the RF output power when the widths of the pulse voltages which are fed to four MOS-FET arrays of the fall-bridged inverter are changed using the pulse width control circuit. The power conversion efficiency of the full-bridged MOS-FET DC-to-RF power inverter was approximately 85 % when the duty cycles of the pulse voltages were changed from 30 % to 50 %. The RF output voltage from the full-bridged MOS-FET DC-to-RF inverter is fed to the rectifier circuit through the output transformer. The rectifier circuit consists of GaAs schottky diodes and filters, each of which is made of a coil and capacitors. The power conversion efficiency of the rectifier circuit was over 80 % when the duty cycles of the pulse voltages were changed from 30 % to 50 %. The output voltage of the rectifier circuit was changed from 34.7V to 37.6 V when the duty cycles of the pulse voltages were changed from 30 % to 50 %.

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Change in Cell Size and Buoyant Density of Pseudomonas diminuta in Response to Osmotic Shocks

  • Lee, So-Hee;Cho, Yu-Ree;Choi, Yong-Jin;Kim, Chan-Wha
    • Journal of Microbiology and Biotechnology
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    • 제11권2호
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    • pp.326-328
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    • 2001
  • Pseudomonas diminuta (ATCC 19146) has been typically used in the bacterial challenge test for validation of the sterilizing filtration process. Cell size is critical for determining the retention characteristics of membrane filters with pore-size of $0.2{\mu}m$. The changes of cell sizes after osmotic shocks at 150, 260, 500, and 700 mosM were measured by a particle size analyzer and the changes of their buoyant densities were analyzed with a Percoll gradient. The results indicated that there were no significant differences when cells were cultured in 260 mosM medium and osmotically shocked at 500 and 700 mosM. However, the osmotically shocked cells at 150 mosM showed a 38% increase of the cell size compared to the cells at 260 mosM. From these study, we concluded that the worst case condition for validation of a sterilizing filter would be 500 mosM, not because of changes in the cell size, but due to decrease in cell viability under those conditions.

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Capacitance-voltage Characteristics of MOS Capacitors with Ge Nanocrystals Embedded in HfO2 Gate Material

  • Park, Byoung-Jun;Lee, Hye-Ryeong;Cho, Kyoung-Ah;Kim, Sang-Sig
    • 한국전기전자재료학회논문지
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    • 제21권8호
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    • pp.699-705
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    • 2008
  • Capacitance versus voltage (C-V) characteristics of Ge-nanocrystal (NC)-embedded metal-oxide-semiconductor (MOS) capacitors with $HfO_2$ gate material were investigated in this work. The current versus voltage (I-V) curves obtained from Ge-NC-embedded MOS capacitors fabricated with the $NH_3$ annealed $HfO_2$ gate material reveal the reduction of leakage current, compared with those of MOS capacitors fabricated with the $O_2$ annealed $HfO_2$ gate material. The C-V curves of the Ge-NC-embedded MOS capacitor with $HfO_2$ gate material annealed in $NH_3$ ambient exhibit counterclockwise hysteresis loop of about 3.45 V memory window when bias voltage was varied from -10 to + 10 V. The observed hysteresis loop indicates the presence of charge storages in the Ge NCs caused by the Fowler-Nordheim (F-N) tunneling. In addition, capacitance versus time characteristics of Ge-NC-embedded MOS capacitors with $HfO_2$ gate material were analyzed to investigate their retention property.

이기종 컴퓨터(MOS/EMS)간 데이터 자동변환시스템 개발 (Development of data conversion system between MOS & EMS)

  • 이강재;최봉수;김태언
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2008년도 제39회 하계학술대회
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    • pp.1863-1864
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    • 2008
  • 한국전력거래소에서 운영중인 EMS(Energy Management System)와 MOS(Market Operation System) 설비는 각각 Alstom사와 ABB사에 의해 우리나라의 전력계통 특성에 맞게 제작되어 공급된 전력계통과 전력시장의 운영을 자동화한 시스템이다. EMS는 전력계통 감시와 효율적인 운영을 위해 전력계통을 모델링한 데이터를 활용하며, MOS는 실시간 급전계획 수립을 위한 기반자료로 전력계통을 모델링한 데이터를 사용하게 된다. 그러나, 대한민국 전력산업의 핵심인 두 시스템은 시스템 설계 방식 및 DB 구조가 상이하여 전력계통의 신.증설 및 변경 시 동일한 데이터를 양 시스템에 각각 따로 구축, 운영해야하는 실정이다. 이에 따라 DB작업을 위한 자료 준비부터 입력, 수정, 검증 등 모든 과정에 중복된 관리가 이루어지고 있다. 중복 관리는 양 시스템 간 DB의 주요 데이터 특성 및 명칭이 상이하여 일률적인 관리가 어렵고, 시스템별 특성 및 운영노하우가 없이는 인적실수에 의한 입력오류 개연성이 폭넓게 존재하는 등 현 상황에서 피할 수 없는 현실이었다. EMS와 MOS 시스템 중 최소한 개의 시스템을 전면 재구축하지 않으면 해결되지 않을 본 문제를 해소하기 위하여 전력거래소는 특정 시스템에 구축된 데이터를 변환알고리즘을 통해 나머지 하나의 시스템에 자동 구축할 수 있는 시스템을 개발하여 활용하고자 한다. 이것이 바로 EMS에 입력되어 정확성이 검증된 계통데이터를 추출하여 MOS의 데이터 형식으로 변환하고, 변환된 데이터를 MOS시스템에 자동으로 입력할 수 있는 MOS/EMS 데이터 자동변환시스템이다.

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