• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.7
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• pp.1218-1223
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• 2007

A surface micro machined angular rate sensor utilizing a vibrating MEMS structure on a silicon has been developed. These tuning fork angular rate sensors are extremely rugged, inherently balanced, and easy to fabricate. The device is fabricated using a temperature compensation method based on automatic gain control technique. A linearity of approximately 0.6%, limited by the on-chip electronics has been obtained with this new sensor. Tests of the sensor demonstrate that its performance is equivalent to that required for implementation of a yaw control system. Vehicle handling and safety are substantially improved using the sensor to implement yaw control.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.3
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• pp.1-6
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• 2016

The Internet of Things (IoT) is a new technology paradigm demanding one packaged system of various semiconductor and MEMS devices. Therefore, the development of electronic packaging technology with very high connectivity is essential for successful IoT applications. This paper discusses both fan-out wafer level packaging (FOWLP) and 3D stacking technologies to achieve the integrattion of heterogeneous devices for IoT. FOWLP has great advantages of high I/O density, high integration, and design flexibility, but ultra-fine pitch redistribution layer (RDL) and molding processes still remain as main challenges to resolve. 3D stacking is an emerging technology solving conventional packaging limits such as size, performance, cost, and scalability. Among various 3D stacking sequences wafer level via after bonding method will provide the highest connectivity with low cost. In addition substrates with ultra-thin thickness, ultra-fine pitch line/space, and low cost are required to improve system performance. The key substrate technologies are embedded trace, passive, and active substrates or ultra-thin coreless substrates.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.226-229
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• 2001

현재 초소형 정밀기계(MEMS;Microelectromechanical System) 소자의 가장 큰 문제점으로 대두되고 있는 점착현상을 방지하기 위하여 불화유기박막을 증착하였다. Octafluorocyclobutane(C$_4$F$_{8}$)을 소스가스를 PECVD (Plasma Enhanced CVD)와 ICP (Inductively Coupled Plasma)를 이용하여 증착하였다. 여기에 Ar을 첨가하여 플라즈마의 반응성을 높여주었다. 형성된 불화유기박막의 나노트라이볼러지 특성을 살펴보기 위하여 AFM을 통하여 증착시킨 시편의 topography를 살펴보았다. 그리고 박막의 antiadhesion의 정도를 살펴보기 위하여 cantilever와 박막의 표면 사이에 존재하는 interaction force를 측정 하였고 AFM의 force curve mode를 이용하였다 PECVB를 이용하여 증착된 박막은 ICP를 이용한 박막보다 균일하지 못한 박막을 보였으며 attractive force가 강한 것으로 사료된다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.41-47
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• 2001

폴리머 박막은 반도체 패키징, MEMS 구조물은 물론 MCM-D 등의 기술에도 널리 쓰이고 있다. 또한 대부분 폴리머/금속의 다층구조의 형태를 띠고 있어 이 상태의 기계적 특성의 이해는 더욱 중요하다. 본 연구에서는 폴리머 박막의 기계적 특성을 측정하기 위한 새로운 방법이 제안된다. 제안된 방법은 최근 발달된 마이크로머시닝기술을 사용하여 구현된 공진형 스트링구조를 이용하게된다. 폴리머 기계적 특성치와 스트링의 공진특성은 서로 상관 관계를 갖게되며 이러한 공진특성의 측정은 기계적 특성의 실시간 관찰을 가능하게 해준다. 본 논문에서는 공진형 스트링을 이용하여 폴리이미드의 잔류음력과 폴리이미드/금속간의 접착 내구성을 정량화하는 방법을 제안한다. 제안된 측정방법은 단순히 스트링구조 뿐만 아니라 다른 기계적 구조에도 응용이 가능하다.

• Journal of Sensor Science and Technology
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• v.14 no.2
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• pp.69-77
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• 2005

The electronic nose (e-nose) has been used in food industry and quality controls in plastic packaging. Recently it finds its applications in medical diagnosis, specifically on detection of diabetes, pulmonary or gastrointestinal problem, or infections by examining odors in the breath or tissues with its odor characterizing ability. Moreover, the use of portable e-nose enables the on-site measurements and analysis of vapors without extra gas-sampling units. This is expected to widen the application of the e-nose in various fields including point-of-care-test or e-health. In this study, a PDA-based portable e-nose was developed using micro-machined gas sensor array and miniaturized electronic interfaces. The rich capacities of the PDA in its computing power and various interfaces are expected to provide the rapid and application specific development of the diagnostic devices, and easy connection to other facilities through information technology (IT) infra. For performance verification of the developed portable e-nose system, Six different vapors were measured using the system. Seven different carbon-black polymer composites were used for the sensor array. The results showed the reproducibility of the measured data and the distinguishable patterns between the vapor species. Additionally, the application of two typical pattern recognition algorithms verified the possibility of the automatic vapor recognition from the portable measurements. These validated the portable e-nose based on PDA developed in this study.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.2
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• pp.49-53
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• 2018

Recently, technologies for integrating various devices such as a flexible device, a transparent device, and a MEMS device have been developed. The key processes of heterogeneous device manufacturing technology are chip or wafer-level bonding process, substrate grinding process, and thin substrate handling process. In this study, the effect of Si substrate grinding process on the electrical properties of tin oxide thin films applied as transparent thin film transistor or flexible electrode material was investigated. As the Si substrate thickness became thinner, the Si d-spacing decreased and strains occurred in the Si lattice. Also, as the Si substrate thickness became thinner, the electric conductivity of tin oxide thin film decreased due to the lower carrier concentration. In the case of the thinner tin oxide thin film, the electrical conductivity was lower than that of the thicker tin oxide thin film and did not change much by the thickness of Si substrate.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.2
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• pp.121-127
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• 2022

Micro-LED is a light-emitting diode smaller than 100 ㎛ in size. It attracts much attention due to its superior performance, such as resolution, brightness, etc., and is considered for various applications like flexible display and VR/AR. Micro-LED display requires a mass transfer process to move micro-LED chips from a LED wafer to a target substrate. In this study, we proposed a vacuum chuck method as a mass transfer technique. The vacuum chuck was fabricated with MEMS technology and PDMS micro-mold process. The spin-coating approach using a dam structure successfully controlled the PDMS mold's thickness. The vacuum test using solder balls instead of micro-LED confirmed the vacuum chuck method as a mass transfer technique.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.55-59
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• 2018

In this paper, we investigated the characteristics of shear stress type piezoresistor on a diaphragm structure formed by MEMS (Microelectromechanical System) technology of silicon-direct-bonding (SDB) wafers with Si/$SiO_2$/Si-sub. The diaphragm structure formed by etching the backside of the wafer using a TMAH aqueous solution can be used for manufacturing various sensors. In this study, the optimum shape condition of the shear stress type piezoresistor formed on the diaphragm is found through ANSYS simulation, and the diaphragm structure is formed by using the semiconductor microfabrication technique and the shear stress formed by boron implantation. The characteristics of the piezoelectric resistance are compared with the simulation results. The sensing diaphragm was made in the shape of an exact square. It has been experimentally found that the maximum shear stress for the same pressure at the center of the edge of the diaphragm is generated when the structure is in the exact square shape. Thus, the sensing part of the sensor has been designed to be placed at the center of the edge of the diaphragm. The prepared shear stress type piezoresistor was in good agreement with the simulation results, and the sensitivity of the piezoresistor formed on the $2200{\mu}m{\times}2200{\mu}m$ diaphragm was $183.7{\mu}V/kPa$ and the linearity of 1.3 %FS at the pressure range of 0~100 kPa and the symmetry of sensitivity was also excellent.

• Transactions of the Society of Information Storage Systems
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• v.2 no.3
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• pp.163-168
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• 2006

Small form factor optical pickup (SFFOP) corresponding to BD specifications is strongly proposed for the next-generation portable storage device. In order to generate SFFOP, small sized optical pickup has been fabricated. We have developed a small sited optical pickup that is called the integrated optical pickup (IOP). The fabrication method of this system is mainly dependant on the use of the wafer based micro fabrication technology, which has been used in MEMS process such as photolithography, reactive ion etching, wafer bonding, and packaging process. This approach has the merits for mass production and high assembling accuracy. In this study, to generate the small sized optical pickup for high recording capacity, IOP corresponding to BD specifications has been designed and developed, including three main parts, 1) design, fabrication and evaluation of objective lens unit, 2) design and fabrication of IOP and 3) evaluation process of FES and TES.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.1-9
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• 2010

Three-dimensional (3-D) integration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip to form highly integrated micro-nano systems. Since CMOS device scaling has stalled, 3D integration technology allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. The potential benefits of 3D integration can vary depending on approach; increased multifunctionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. It is expected that the semiconductor industry's paradiam will be shift to a new industry-fusing technology era that will offer tremendous global opportunities for expanded use of 3D based technologies in highly integrated systems. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of IT-NT-BT systems. This paper attempts to introduce new 3D integration technologies of the chip self-assembling stacking and 3D heterogeneous opto-electronics integration for realizng the super-chip.