• Journal of Sensor Science and Technology
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• v.15 no.2
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• pp.112-119
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• 2006

Resolution of an image sensor is very significant parameter to improve. It is hard to improve the resolution of the CMOS vision chip for edge detection based on a biological retina using a resistive network because the vision chip contains additional circuits such as a resistive network and some processing circuits comparing with general image sensors such as CMOS image sensor (CIS). In this paper, we proved the problem of low resolution by separating photo-sensing and signal processing circuits. This type of vision chips occurs a problem of low operation speed because the signal processing circuits should be commonly used in a row of the photo-sensors. The low speed problem of operation was proved by using a reset decoder. A vision chip for edge detection with $128{\times}128$ pixel array has been designed and fabricated by using $0.35{\mu}m$ 2-poly 4-metal CMOS technology. The fabricated chip was integrated with optical lens as a camera system and investigated with real image. By using this chip, we could achieved sufficient edge images for real application.

• Journal of East-West Nursing Research
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• v.13 no.1
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• pp.48-56
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• 2007

Purpose: This is a descriptive research to examine the levels of ADL, self efficacy, and life satisfaction of elderly institution residents, and the relations among the factors. Method: Data were collected through a questionnaire survey of elders aged over 65 at nursing homes in 9 areas throughout the country. Measures were the physical function scale, the general self efficacy scale, and LSI Z. Collected data were analyzed using SAS/PC11.0. Result: First, the mean levels of ADL, self efficacy, and life satisfaction were 2.83 (0.85), 2.79 (0.63), and 1.18 (0.42). Second, the relations among three factors were showed positive correlations. Third, (1) The level of ADL was statistically significantly different according to health condition, religious activity, volunteer activity, and friend meeting. (2) The level of self efficacy was statistically significantly different according to health condition, source of help, religious activity, volunteer activity, friend meeting, and elderly school & senior center. (3) The level of life satisfaction was statistically significantly different according to health condition, source of help, religious activity, volunteer activity, friend meeting, and elderly school & senior center. Conclusion: Conclusively, it is required to enhance ADL and self-efficacy in order to improve elderly institution residents’ life satisfaction.

• Asian Pacific Journal of Cancer Prevention
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• v.16 no.16
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• pp.7219-7229
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• 2015

Background: Chromosomal aberrations identified in acute lymphoblastic leukemia (ALL) have an important role in disease diagnosis, prognosis and management. Information on karyotype and associated clinical parameters are essential to physicians for planning cancer control interventions in different geographical regions. Materials and Methods: In this study, we present the overall frequency and distribution patterns of chromosomal aberrations in both children and adult de novo B lineage ALL Indian patients using conventional cytogenetics, interphase FISH and multiplex RT-PCR. Results: Among the 215 subjects, cytogenetic results were achieved in 172 (80%) patients; normal karyotype represented 37.2% and abnormal 62.8% with a distribution as follows: 15.3% hypodiploidy; 10.3% hyperdiploidy; 15.8% t(9;22); 9.8% t(1;19); 3.7% t(12;21); 2.8% t(4;11); 2.8% complex karyotypes. Apart from these, we observed several novel, rare and common chromosomal rearrangements. Also, FISH studies using LSI extra-signal dual-color probes revealed additional structural or numerical changes. Conclusions: These results demonstrate cytogenetic heterogeneity of ALL and confirm that the incidence of chromosomal abnormalities varies considerably. To the best of our knowledge, this is one of the largest reported series of cytogenetic investigations in Indian B-lineage ALL cases. In addition, ongoing cytogenetic studies are warranted in larger groups of B-lineage ALL cases to identify newly acquired chromosomal abnormalities that may contribute to disease diagnosis and management.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.176- 184
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• 2010

A low-power inductorless 1:4 DEMUX and a 4:1 MUX for a 90 nm CMOS are presented. The DEMUX can be operated at a speed of 25 Gb/s with the power supply voltage of 1.05 V, and the power consumption is 8.9 mW. The area of the DEMUX core is $29\;{\times}\;40\;{\mu}m^2$. The operation speed of the 4:1 MUX is 13 Gb/s at a power supply voltage of 1.2 V, and the power consumption is 4 mW. The area of the MUX core is $30\;{\times}\;18\;{\mu}m^2$. The MUX/DEMUX mainly consists of differential pseudo-NMOS. In these MUX/DEMUX circuits, logic swing is nearly rail-to-rail, and a low $V_{dd}$. The component circuit is more scalable than a CML circuit, which is commonly used in a high-performance MUX/DEMUX. These MUX/DEMUX circuits are compatible with conventional CMOS logic circuit, and it can be directly connected to CMOS logic gates without logic level conversion. Furthermore, the circuits are useful for core-to-core interconnection in the system LSI or chip-to-chip communication within a multi-chip module, because of its low power, small footprint, and reasonable operation speed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.71-77
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• 2009

A novel phase-locked loop(PLL) architecture with multiple charge pumps for fast locking has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. The fast locking PLL that changes its loop bandwidth through controlling charge pumps depending on locking status has been designed. The capacitor usually occupying the larger portion of the chip is also minimized with the proposed scheme. Therefore, the PLL size of $990{\mu}m\;{\times}\;670{\mu}m$ including resistors and capacitors at the bandwidth of 29.9KHz has been achieved. It has been fabricated with 3.3V $0.35{\mu}m$ CMOS process. The locking time is less than $6{\mu}s$ with the measured phase noise of -90.45dBc/Hz @1MHz at 851.2MHz output frequency.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.1
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• pp.529-536
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• 2011

In this study, we confirmed that the SWRO(Sea Water Reverse Osmosis) production water has more hard corrosiveness than the tap water by fundamental experiment. According to the result, the target of this study was aimed at developing maintenance and anti-corrosion method. In the early stages of the research, batch tests using mild steel coupons and electrochemical experiments were applied to compare the corrosiveness between SWRO production water and the tap water. After then, two corrosion control methods for SWRO production water were applied. Liquid lime($Ca(OH)_2$) and Carbon Dioxide($CO_2$) were inserted and compared with the combination of liquid lime with phosphate corrosion inhibitor and carbon dioxide. The water qualities were evaluated through LSI(Langelier Saturation Index) and proper injection ratio was deduced by the result. Since then, simulated loop system test were performed to evaluate anti-corrosion effect depending on corrosion inhibitors. Subsequently, carbon steel pipes equipped at the loop system were detached for SEM, EDX and XRD analysis to acquire quantitative and qualitative data of the major corrosion products inside the pipes. In conclusion, the controled groups with anti-corrosion techniques applied were effective by appearing 97.4% and 90.9% of improvements in both case of liquid lime and the liquid lime with a phosphate corrosion Inhibitor. furthermore, major components of scale were iron oxides, on the other hand, protective effect of film formation by calcium carbonate($CaCO_3$) could be confirmed.

• Korean Journal of Environment and Ecology
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• v.37 no.4
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• pp.289-301
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• 2023

Forests within watersheds are essential in maintaining ecosystems and are the central infrastructure for constructing an ecological network system. However, due to indiscriminate development projects carried out over past decades, forest fragmentation and land use changes have accelerated, and their original functions have been lost. Since a forest's structural pattern directly impacts ecological processes and functions in understanding forest ecosystems, identifying and analyzing change patterns is essential. Therefore, this study analyzed structural changes in the forest landscape according to the time-series land cover changes using the FRAGSTATS model for the dam watershed of the Geum River upstream. Land cover changes in the dam watershed of the Geum River upstream through land cover change detection showed an increase of 33.12 square kilometers (0.62%) of forests and 67.26 square kilometers (1.26%) of urbanized dry areas and a decrease of 148.25 square kilometers (2.79%) in agricultural areas from the 1980s to the 2010s. The results of no-sampling forest landscape analysis within the watershed indicated landscape percentage (PLAND), area-weighted proximity index (CONTIG_AM), average central area (CORE_MN), and adjacency index (PLADJ) increased, and the number of patches (NP), landscape shape index (LSI), and cohesion index (COHESION) decreased. Identification of structural change patterns through a moving window analysis showed the forest landscape in Sangju City, Gyeongsangbuk Province, Boeun County in Chungcheongbuk Province, and Jinan Province in Jeollabuk Province was relatively well preserved, but fragmentation was ongoing at the border between Okcheon County in Chungcheongbuk Province, Yeongdong and Geumsan Counties in Chungcheongnam Province, and the forest landscape in areas adjacent to Muju and Jangsu Counties in Jeollabuk Province. The results indicate that it is necessary to establish afforestation projects for fragmented areas when preparing a future regional forest management strategy. This study derived areas where fragmentation of forest landscapes is expected and the results may be used as basic data for assessing the health of watershed forests and establishing management plans.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.378-386
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• 2017

A return-to-zero (RZ) digital-to-analog converter (DAC) with a tri-state switching scheme is proposed in this paper. The proposed scheme provides a triple weight output for RZ operation by using a conventional differential current switch and simple pseudo-differential F/Fs. The RZ function is realized with only two additional transistors in each F/F cell, which results in a power dissipation increase of less than 5%. To verify the performance of the proposed method, a 10-bit RZ DAC is fabricated using standard 180-nm CMOS technology. Measured results show that the worst SFDR performances are 60 dBc and 55 dBc in the 1st and 2nd Nyquist bands, respectively, when operating at 650 MHz clock frequency. The total power consumption is 64 mW, and the active area occupies $0.25mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.139-145
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• 2014

Control of threshold voltage ($V_T$) by ground-plane (GP) technique for planar tunnel field-effect transistor (TFET) is studied for the first time using TCAD simulation method. Although GP technique appears to be similarly useful for the TFET as for the metal-oxide-semiconductor field-effect transistor (MOSFET), some unique behaviors such as the small controllability under weak ground doping and dependence on the dopant polarity are also observed. For $V_T$-modulation larger than 100 mV, heavy ground doping over $1{\times}10^{20}cm^{-3}$ or back biasing scheme is preferred in case of TFETs. Polarity dependence is explained with a mechanism similar to the punch-through of MOSFETs. In spite of some minor differences, this result shows that both MOSFETs and TFETs can share common $V_T$-control scheme when these devices are co-integrated.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.129-140
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• 2017

In this paper, a $4{\times}32$-channel neural recording system capable of acquiring neural signals is introduced. Four 32-channel neural recording ICs, complex programmable logic devices (CPLDs), a micro controller unit (MCU) with USB interface, and a PC are used. Each neural recording IC, implemented in $0.18{\mu}m$ CMOS technology, includes 32 channels of analog front-ends (AFEs), a 32-to-1 analog multiplexer, and an analog-to-digital converter (ADC). The mid-band gain of the AFE is adjustable in four steps, and have a tunable bandwidth. The AFE has a mid-band gain of 54.5 dB to 65.7 dB and a bandwidth of 35.3 Hz to 5.8 kHz. The high-pass cutoff frequency of the AFE varies from 18.6 Hz to 154.7 Hz. The input-referred noise (IRN) of the AFE is $10.2{\mu}V_{rms}$. A high-resolution, low-power ADC with a high conversion speed achieves a signal-to-noise and distortion ratio (SNDR) of 50.63 dB and a spurious-free dynamic range (SFDR) of 63.88 dB, at a sampling-rate of 2.5 MS/s. The effectiveness of our neural recording system is validated in in-vivo recording of the primary somatosensory cortex of a rat.