• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.47-50
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• 2001

Nowadays ARM7 core is used in many fields such as PDA systems because of the low power and low cost. It is a general-purpose processor, designed for both efficient digital signal processing and controller operations. But the advent of the wireless communication creates a need for high computational performance for signal processing. And then This paper has been designed a floating-point multiplier compatible to IEEE-754 single precision format for ARMTTDMI performance improvement.

• The KIPS Transactions:PartA
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• v.11A no.7 s.91
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• pp.489-498
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• 2004

VLIW processor is considered to be an appropriate processor for the embedded system, provided with high performance and low power con-sumption due to its simple hardware structure. Unfortunately, the VLIW processor often suffers from high memory access latency due to the variable length of I-packets, which consist of independent instructions to be issued in parallel. It is because of the variable I-packet length that some I-packets must be placed over two cache blocks, which are called straddle I-packets, so that two cache accesses are required to fetch such I-packets. In this paper, an expansion buffer cache is proposed to improve not only the instruction fetch bandwidth, but also the power consumption of the I-cache with moderate hardware cost. The expansion buffer cache has a small expansion buffer containing a fraction of a straddle packet along with the main cache to reduce the additional cache accesses due to the straddle I-packets. With a great reduction in the cache accesses due to the straddle packets, the expansion buffer cache can achieve $5{\~}9{\%}$improvement over the conventional I-caches in the $Delay{\cdot}Power{\cdot}Area$ metric.

• Journal of Power Electronics
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• v.7 no.2
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• pp.174-180
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• 2007

In this paper, a simple control method for two-stage utility grid-connected photovoltaic power conditioning systems (PCS) is proposed. This approach enables maximum power point (MPP) tracking control with post-stage inverter current information instead of calculating solar array power, which significantly simplifies the controller and the sensor. Furthermore, there is no feedback loop in the pre-stage converter to control the solar array voltage or current because the MPP tracker drives the converter switch duty cycle. This simple PCS control strategy can reduce the cost and size, and can be utilized with a low cost digital processor. For verification of the proposed control strategy, a 2.5kW two-stage photovoltaic grid-connected PCS hardware which consists of a boost converter cascaded with a single-phase inverter was built and tested.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.97-101
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• 2013

There is a growing need for optical communication systems that convert large volumes of data to optical signals and that accommodate and transmit the signals across long distances. Digital optical communication consists of a master unit (MU) and a slave unit (SU). The MU transmits data to SU using digital optical signals. However, digital optical units that are commercially available or are under development transmit data using two's complement representation. At low input levels, a large number of SSOs (simultaneous switching outputs) are required because of the high rate of bit switching in two's complement, which thereby increases the power noise. This problem reduces the overall system capability because a DSP (digital signal processor) chip (FPGA, CPLD, etc.) cannot be used efficiently and power noise increases. This paper proposes a change from two's complement to a more efficient method that produces less SSO noise and can be applied to existing digital optical units.

• ETRI Journal
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• v.29 no.1
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• pp.79-88
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• 2007

This paper proposes a novel concept of adjusting the hardware size in a multi-carrier code division multiple access (MC-CDMA) receiver in real time as per the channel parameters such as delay spread, signal-to-noise ratio, transmission rate, and Doppler frequency. The fast Fourier transform (FFT) or inverse FFT (IFFT) size in orthogonal frequency division multiplexing (OFDM)/MC-CDMA transceivers varies from 1024 points to 16 points. Two low-power reconfigurable radix-4 256-point FFT processor architectures are proposed that can also be dynamically configured as 64-point and 16-point as per the channel parameters to prove the concept. By tailoring the clock of the higher FFT stages for longer FFTs and switching to shorter FFTs from longer FFTs, significant power saving is achieved. In addition, two 256 sub-carrier MC-CDMA receiver architectures are proposed which can also be configured for 64 sub-carriers in real time to prove the feasibility of the concept over the whole receiver.

• Journal of Power Electronics
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• v.5 no.1
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• pp.11-19
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• 2005

This paper describes the two control techniques to perform the sensorless vector control of a PMSM by injecting the high frequency voltage to the stator terminal. The first technique is the estimation algorithm of the initial rotor position. A PMSM possesses the saliency which produces the ellipse of the stator current when the high frequency voltage is injected into the motor terminal. The major axis angle of the current ellipse gives the rotor position information at a standstill. The second control technique is a sensorless control algorithm that injects the high frequency voltage to the stator terminal in order to estimate the rotor position and speed. The rotor position and speed for sensorless vector control is calculated by appropriate signal processing to extract the position information from the stator current at low speeds or standstill. The proposed sensorless algorithm using the double-band hysteresis controller exhibits excellent reference tracking and increased robustness. Experimental results are presented to verify the feasibility of the proposed control schemes. Speed, position estimation and vector control were carried out on the floating point processor TMS320VC33.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1545-1552
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• 2013

This paper presents an implementation of embedded platform based ARM A8-cortex processor for android supporting. The development board for S5PV210 is a platform that is suitable for code development of SAMSUNG's S5PV210 32bit RICS micro controller(ARMv7) architecture for hand-held device and general applications. Embedded platform development board offers various function and high efficiencies. In addition to the high performance, the embedded platform offers low current consumption, ensuring low costs and power.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2005.06a
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• pp.1011-1015
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• 2005

Fully digital controlled 20-bit magnet power supplies have been developed and successfully tested for closed orbit correction of PLS(Pohang Light Source). The new digital power supply has used fiber optics for 25kHz switching of IGBT drivers, and implemented DSP, ADC, Interlock, DCCT cards in a compact 3U-sized 19" chassis. Input/Output low-pass filters suppress harmonics of 60Hz line frequency and switching frequency noise effectively. Overall performance of the power supplies have been demonstrated as +/- 2ppm short-term stability(<1 min), and +/- 10ppm long-term stability(<36 hours). All the existing 12-bit 70 power supplies for vertical correction magnets will be replaced with new digital power supplies during 2005 summer shutdown period. In this paper, we will describe the hardware structure and control method of the digital power supply and the experimental results will be shown.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.8
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• pp.1877-1884
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• 2014

Because of the limited power resource, we need a reliable low-power media access control technique suitable for unmaned remote sensor operation condition for the unmanned sensor processor to perform the task in the remote wireless network situation. Therefore CSMA/CA and X-MAC is generally considered to effectively transmit the signal in the low-power wireless network. In this paper, we propose the more efficient low-power LP-MAC Technique which consumes the minimum power and transmits the data faster in condition that the mobile nodes' joining to and leaving from the network which consists of the fixed nodes is fluid. The fixed nodes operate in an asynchronous mode to perform the network self-configuration and transmit data faster to the mobile node which is frequently join and leave the network. When the mobile node leaves the network, the network's operation mode will be synchronous mode to achieve the minimum power consumption, thus the minimum power operation becomes possible.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11A
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• pp.1117-1123
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• 2008

Applications for mobile multimedia are testing the performance limits of present day CPUs with variety. However, hardwired solutions are inflexible and expensive to develop. CPUs with flexibility have limitation of performance. So, the requirement for both ASIC-like performance and CPU-like flexibility has led to reconfigurable processor. Mobile systems require low power and high performance concurrently. In this paper, we propose reconfigurable processor for mobile multimedia with high energy efficiency. Reconfigurable processor with 121MOPS/mW is developed by 130nm CMOS technology. And the processor was simulated for energy efficiency with 539MOPS/mW by 90nm CMOS technology and effective use of instructions. And we tested its applications for multimedia field. We tested the case of inverse MDCT for MP3 and DF for MPEG4 and ME for H.264.