• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.2
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• pp.143-150
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• 2003

An improved MPPT converter with current compensation method for small-scaled PV-applications is presented in this paper. The proposed method implements maximum power point tracking (MPPT) by variable reference current which is continuously changed during one sampling period. Therefore, the Power transferred to the load is increased above 9% by the proposed MPPT converter with current compensation method. As a result, the utilization efficiency of Photovoltaic (PV)-panel can be increased. In addition, as it doesn't use digital signal processor (DSP), this MPPT method has the merits of both a cost efficiency and a simple control circuit design. Therefore, it is considered that the proposed MPPT method is proper to low power, low cost PV-applications. The concept and control principles of the proposed Un moth()d are explained in detail and its validity of the proposed method is verified through several simulated results.

• Journal of Broadcast Engineering
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• v.10 no.1 s.26
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• pp.77-82
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• 2005

We propose a highly Integrated motion estimation processor (MEP) for efficient video compression in an SoC platform. When compressing video by the standards like MPEG-4 and H.263, the macroblock related functions motion compensation. mode decision, motion vector prediction, and motion vector difference calculation require the frequent intervention of MCU. Thus the proposed MEP incorporates those functions with the motion estimation capability to reduce the number of interrupts to MCU, which can lead to a highly efficient SoC system. For low-power consumption, the proposed MEP can prevent the temporally static area from motion estimation or can skip the half-pel motion estimation for those macroblocks whose modes are decided as INTRA.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.551-552
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• 2006

The miniature fuel cells have emerged as a promising power source for applications such as cellular phones, small digital devices, and autonomous sensors to embedded monitors or to micro-electro mechanical system (MEMS) devices. Several chemicals run candidate at a fuel in those systems, such as hydrogen. methanol, ethanol, acetic acid, and di-methyl ether (DME). Among them, hydrogen shows most efficient fuel performance. However, there are some difficulties in practical application for portable power sources. Therefore, more recently, there have been many efforts for development of micro-reformer to operate highly efficient micro fuel cells with liquid fuels such as methanol, ethanol, and DME In our experiments, we have integrated a micro-fuel processor system using low temperature co-fired ceramics (LTCC) materials. Our integrated micro-fuel processor system is containing embedded heaters, cavities, and 3D structures of micro- channels within LTCC layers for embedding catalysts (cf. Figs. 1 and 2). In the micro-channels of LTCC, we have loaded $CuO/ZnO/Al_2O_3$ catalysts using several different coating methods such as powder packing or spraying, dipping, and washing of catalyst slurry.

• Journal of the Korea Society of Computer and Information
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• v.17 no.6
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• pp.1-11
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• 2012

As the process technology scales down, multi-core processors cause serious problems such as increased interconnection delay, high power consumption and thermal problems. To solve the problems in 2D multi-core processors, researchers have focused on the 3D multi-core processor architecture. Compared to the 2D multi-core processor, the 3D multi-core processor decreases interconnection delay by reducing wire length significantly, since each core on different layers is connected using vertical through-silicon via(TSV). However, the power density in the 3D multi-core processor is increased dramatically compared to that in the 2D multi-core processor, because multiple cores are stacked vertically. Unfortunately, increased power density causes thermal problems, resulting in high cooling cost, negative impact on the reliability. Therefore, temperature should be considered together with performance in designing 3D multi-core processors. In this work, we analyze the temperature of the cache in quad-core processors varying cache organization. Then, we propose the low-temperature cache organization to overcome the thermal problems. Our evaluation shows that peak temperature of the instruction cache is lower than threshold. The peak temperature of the data cache is higher than threshold when the cache is composed of many ways. According to the results, our proposed cache organization not only efficiently reduces the peak temperature but also reduces the performance degradation for 3D quad-core processors.

• Journal of Platform Technology
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• v.12 no.2
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• pp.58-63
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• 2024

CNNs tend to take a long time to learn and consume a lot of power due to lack of system resources with many data processing units when there are repetitive handles that do not have high performance in the image field. In this paper, we propose a handling method based on a low-power bus that can increase the exchange rate of multipliers and multiplicands within the convolution mixer, which is a tendency activity that occurs when a convolution mixer has multiplication, which is the core element of combination. Convolutional neural networks have proprietary low-power shared processor support and the design was implemented on an Intel DE1-SoC FPGA board using Verilog-HDL. The experiments validated the performance by comparing it with the exchange rate of the multiplier originally proposed by Shen on MNIST's numeric image database.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.121-124
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• 2004

In this paper, Simple and inexpensive analog maximum power point tracker (MPPT) algorithm for photovoltaic power system and low power system of doesn't use digital signal processor (DSP). The control circuit is composed such that the actual current and voltage are sensed directly from the PV array. These two signals are then multiplied by a single-chip multiplier. The multiplier output go through different time constants genesis pulse width modulated to switch. Finally those were verified through simulation.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.580-583
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• 2002

An improved MPPT converter with current compensation method for small-scaled PV-applications is presented in this paper. The proposed method implements maximum power point tracking (MPPT) by variable reference current which is continuously changed during one sampling period. Therefore, the power transferred to the load is increased above $9\%$ by the proposed MPPT converter with current compensation method. As a result, the utilization efficiency of Photovoltaic (PV)-panel can be increased. In addition, as it doesn't use digital signal processor (DSP), this MPPT method has the merits of both a cost efficiency and a simple control circuit design. Therefore, it is considered that the proposed MPPT method is proper to low power, low cost PV-applications. The concept and control principles of the proposed MPPT method are explained in detail and its validity of the proposed method is verified through several simulated results.

• Journal of Digital Contents Society
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• v.14 no.1
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• pp.59-64
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• 2013

In this paper, we proposed low power algorithm for a task. The task means the inside of a necessary processor and external resources to work accomplishment of a system. Each task analyzes a life time and a number of called for implement a low power circuit. First of all, reduce power consumption of a task have maximum power consumption for low power circuit implementation. Therefore, first selecting a task had maximum power consumption. The task had a maximum power consumption ranking consider a life time and a number of called for each task. While a life time of task is long, top priority ranking to decrease power consumption to the task that the number of call generates the power consumption how a disguise is large in case of a lot of task becomes. Frequency decision to have minimum power consumption, and decrease power consumption all the circuit by a change of frequency of the task which the minimum task that a wasting past record is the maximum becomes. Also, keep continuously minimum power consumption, with every effort task until last life time in opening life time, and decrease gets total power consumption. Experiments results show reduction in the power consumption by 5.43% comparing with that [7] algorithm.

• Convergence Security Journal
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• v.15 no.2
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• pp.81-89
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• 2015

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a key scheduler that employs the presented LFSR and reverse LFSR that can generate four outputs simultaneously. In addition, we construct new key scheduler that generates 4 subkey bytes at a clock since each round block requires 4 subkey bytes at a time. Thus, the entire HIGHT processor can be controlled by single system clock with regular control mechanism. We synthesize the HIGHT processor using the VHDL. From the synthesis results, the logic size of the presented key scheduler can be reduced as 9% compared to the counterpart that is employed in the conventional HIGHT processor.

• The Journal of the Korea Contents Association
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• v.10 no.1
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• pp.103-113
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• 2010

The basic real-time scheduling algorithms based on RM or EDF approaches assume that the tasks are preemptive, but the tasks may contain nonpreemptive sections in many cases. Also the existing scheduling algorithm for reducing the power consumption of the processor is based on the task utilizations and determines the processor speed $S_H$ or $S_L$ according to the existence of the blocking intervals. In this algorithm, the $S_H$ interval that operates in high speed is the interval during which the priority inversion by blocking occurs, and the length of this interval is set to the task deadline that includes the blocking intervals. In this paper, we propose an improved algorithm that can reduce the power consumption ratio by shortening the length of the $S_H$ interval. The simulation shows that the power consumption ratio of the proposed algorithm is reduced as much as 13% compared to the existing one.