1 |
Kim. Jae Jin, Kang. Jin Gu, Hur. Hwa Ra, Yun. Choong Mo," A Frequency Selection Algorithm for Power Consumption Minimization of Processor in Mobile System", The Journal of Korea Society of Digital Industry and Information Management, vol. 4, No.1, pp. 9-16, 2008
|
2 |
Kim. Jae Jin, "A Study of Low Power Algorithm for a Task under the Time Constraint", The Journal of Korea Institute of Information Technology, vol. 7, No. 6, pp. 27-34, 2009
|
3 |
Youn. Choong Mo, Kim. Jae Jin, "A study of FPGA Algorithm for consider the Power Consumption", Journal of Digital Contents Society, vol. 13, No. 1, pp.37-41, 2012
과학기술학회마을
DOI
ScienceOn
|
4 |
A. Chandrakasan, R. Brodersen, "Low power digital CMOS design," Kluwer Academic Publishers, 1995.
|
5 |
Qing Wu, Massoud Pedram, Xunwei Wu, "Clock-Gating and Its Application to Low Power Design of Sequential Circuits," IEEE Custom Interated Circuits Conference, pp.479-482, 1997.
|
6 |
D. Garrett, M. Stan, and A. Dean, "Challenges in clock gating for a low-power ASIC methodology, " in Proc. ISLPED, San Diego, CA, pp. 176-181, August, 1999
|
7 |
T.Mudge, "power:a first-class architectural design constraint, " IEEE COMPUT., vol. 34, no. 4, p.52-58, April, 2001
|
8 |
Padamnabhan Pillai, Kang G. Shin, "Real time Dynamic voltage scaling for low power embedded operating system", In Proceeding of the 18th ACM symposium on Operating System Principles(SOSP-01), pp.89-102, 2001
|
9 |
Pietro Babighian, Enrico Macii, "A Scalable Algorithm for RTL Insertion of Gated Clocks Based on ODCs Computation, " IEEE transactions on Computer-Aided Design of Integrated Circuits And Systems, vol.24, no. 1, pp.29-42, Jaunuary 2005
DOI
ScienceOn
|