Browse > Article
http://dx.doi.org/10.9728/dcs.2013.14.1.59

A Study on the Low Power Algorithm for a Task  

Kim, Jae-Jin (강동대학교 신재생에너지과)
Publication Information
Journal of Digital Contents Society / v.14, no.1, 2013 , pp. 59-64 More about this Journal
Abstract
In this paper, we proposed low power algorithm for a task. The task means the inside of a necessary processor and external resources to work accomplishment of a system. Each task analyzes a life time and a number of called for implement a low power circuit. First of all, reduce power consumption of a task have maximum power consumption for low power circuit implementation. Therefore, first selecting a task had maximum power consumption. The task had a maximum power consumption ranking consider a life time and a number of called for each task. While a life time of task is long, top priority ranking to decrease power consumption to the task that the number of call generates the power consumption how a disguise is large in case of a lot of task becomes. Frequency decision to have minimum power consumption, and decrease power consumption all the circuit by a change of frequency of the task which the minimum task that a wasting past record is the maximum becomes. Also, keep continuously minimum power consumption, with every effort task until last life time in opening life time, and decrease gets total power consumption. Experiments results show reduction in the power consumption by 5.43% comparing with that [7] algorithm.
Keywords
power consumption; Low power; Task; The Life time; The number of call;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 Kim. Jae Jin, Kang. Jin Gu, Hur. Hwa Ra, Yun. Choong Mo," A Frequency Selection Algorithm for Power Consumption Minimization of Processor in Mobile System", The Journal of Korea Society of Digital Industry and Information Management, vol. 4, No.1, pp. 9-16, 2008
2 Kim. Jae Jin, "A Study of Low Power Algorithm for a Task under the Time Constraint", The Journal of Korea Institute of Information Technology, vol. 7, No. 6, pp. 27-34, 2009
3 Youn. Choong Mo, Kim. Jae Jin, "A study of FPGA Algorithm for consider the Power Consumption", Journal of Digital Contents Society, vol. 13, No. 1, pp.37-41, 2012   과학기술학회마을   DOI   ScienceOn
4 A. Chandrakasan, R. Brodersen, "Low power digital CMOS design," Kluwer Academic Publishers, 1995.
5 Qing Wu, Massoud Pedram, Xunwei Wu, "Clock-Gating and Its Application to Low Power Design of Sequential Circuits," IEEE Custom Interated Circuits Conference, pp.479-482, 1997.
6 D. Garrett, M. Stan, and A. Dean, "Challenges in clock gating for a low-power ASIC methodology, " in Proc. ISLPED, San Diego, CA, pp. 176-181, August, 1999
7 T.Mudge, "power:a first-class architectural design constraint, " IEEE COMPUT., vol. 34, no. 4, p.52-58, April, 2001
8 Padamnabhan Pillai, Kang G. Shin, "Real time Dynamic voltage scaling for low power embedded operating system", In Proceeding of the 18th ACM symposium on Operating System Principles(SOSP-01), pp.89-102, 2001
9 Pietro Babighian, Enrico Macii, "A Scalable Algorithm for RTL Insertion of Gated Clocks Based on ODCs Computation, " IEEE transactions on Computer-Aided Design of Integrated Circuits And Systems, vol.24, no. 1, pp.29-42, Jaunuary 2005   DOI   ScienceOn