• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.8
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• pp.1465-1470
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• 2006

This paper presents a design of low power CMOS LNA(Low Noise Amplifier) for 2.4 GHz ZigBee applications that is a promising international standard for short area wireless communications. The proposed circuit has been designed using TSMC $0.18{\mu}m$ CMOS process technology and two stage cascade topology by current reuse technique. Two stage cascade amplifiers use the same bias current in the current reused stage which leads to the reduction of the power dissipation. LNA design procedures and the simulation results using ADS(Advanced Design System) are presented in this paper. Simulation results show that the LNA has a extremely low power dissipation of 1.38mW with a supply voltage of 1.0V. This is the lowest value among LNAs ever reported. The LNA also has a maximum gain of 13.38dB, input return loss of -20.37dB, output return loss of -22.48dB and minimum noise figure of 1.13dB.

• Journal of electromagnetic engineering and science
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• v.11 no.1
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• pp.27-33
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• 2011

In this paper, we propose a high gain, current reused ultra wideband (UWB) low noise amplifier (LNA) that uses TSMC 0.18 ${\mu}m$ CMOS technology. To satisfy the wide input matching and high voltage gain requirements with low power consumption, a resistive current reused technique is utilized in the first stage. A ${\pi}$-type LC network is adopted in the second stage to achieve sufficient gain over the entire frequency band. The proposed UWB LNA has a voltage gain of 12.9~18.1 dB and a noise figure (NF) of 4.05~6.21 dB over the frequency band of interest (1~10 GHz). The total power consumption of the proposed UWB LNA is 10.1 mW from a 1.4 V supply voltage, and the chip area is $0.95{\times}0.9$ mm.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.4
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• pp.121-127
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• 2024

In this paper, FEM (Front-End Module) MMIC, a key component for the application of the satellite communication terminal transmission and reception module of the multi-phase array structure, was designed and verified as a single chip by designing the Power Amplifier (PA) and the Low Noise Amplifier (LNA). It was manufactured using the GaAs PP10 (100nm) process, a compound semiconductor process from Win-semiconductors, and the operating frequency band of 7.2-10.5GHz operation, output 1W, and noise index of 1.5dB or less were secured using a dedicated test board. The developed FEM MMIC can be used as a single chip, and the components PA and LNA can also be used as each device. The developed device will be used in various applications of Minsu/Gunsu using the X band and the localization of overseas parts.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.505-506
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• 2006

In this paper, the linearization technique for CMOS low-noise amplifier (LNA) using the derivative superposition method through the multiple gated transistors configuration is presented. LNA based on 0.13um RF CMOS process has been implemented with a modified cascode configuration using multiple gated common source transistors to fulfill a high linearity. Compared with a conventional cascode type LNA, the third order input intercept point (IIP3) per DC power consumption (IIP3/DC) is improved by 3.85 dB. The LNA achieved 2.5-dBm IIP3 with 13.4-dB gain, 3.6 dB NF at 2.4 GHz consuming 8.56 mA from a 1.5-V supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.995-998
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• 2005

This paper proposes a new SoC (System-on-Chip)-based automatic compensation circuit (ACC) for 5GHz low noise amplifier (LNA). This circuit is extremely useful for today's RF IC (Radio Frequency Integrated Circuit) devices in a complete RF transceiver environment. The circuit contains RF BIST (Built-ln Self-Test) circuit, Capacitor Mirror Banks (CMB) and digital processing unit (DPU). The ACC automatically adjusts performance of 5GHz LNA by the processor in the SoC transceiver when the LNA goes out of the normal range of operation.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.11a
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• pp.61-64
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• 2000

We fabricated and characterized Low Noise Amplifier (LNA) using MCM-C (Multi-Chip-Module-Cofired) technology for 2.14 GHz IMT-2000 mobile terminal application. First, We designed LNA circuits and simulated it's high frequency characteristics using circuits simulator. For the simulation, we adopted high frequency libraries of all the devices used in LNA samples. By the simulation, Gain was 17 dB and Noise Figure was 1.4 dB. We used multilayer process of LTCC (Low Temperature Co-fired Ceramics) substrate and conductor, resistor pattern for the MCM-C LNA fabrication. We made 2 buried inductors, 2 buried capacitors and 3 buried resistors. The number of the total layers was 6. On the top layer, we patterned microstrip line and pads for the SMT device. We measured the high frequency characteristics, and the results were 14.7 dB Gain and 1.5 dB Noise Figure.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.900-905
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• 2009

A common drain feedback CMOS wideband LNA with current bleeding and input inductive series-peaking techniques is presented in this paper. DC coupling is adopted between cascode and feedback amplifiers, so that the gain and NF of the LNA can be dynamically controlled by adjusting the bleeding current. The fabricated LNA shows the bandwidth of 2.5 GHz. The high gain mode shows 17.5 dB gain with $1.7{\sim}2.8\;dB$ NF and consumes 27 mW power and the low gain mode has 14 dB gain with $2.7{\sim}4.0\;dB$ NF and dissipates 1.8 mW from 1.8 V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.1
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• pp.67-76
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• 2000

In this paper, a low noise amplifier has been developed, which is operating at L-band i.e., 1525-1575 MHz. By using resistive decoupling circuits, the resistor dissipates undesired signal in low frequency band. By adopting this design method the stability of the LNA is increased and the input impedance matching is improved. The LNA consists of the low noise GaAs FET ATF-10136 and the internally matched VNA-25. The low LNA is fabricated by both the RP circuit and the self-bias circuits in an aluminum housing. As a result, the characteristics of the LNA implemented show more than 32 dB in gain, lower than 0.5 dB in noise figure, 18.6 dBm output gain in 1 dB gain compression point.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.654-657
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• 2002

This paper introduces the design and implementation of 40-㎓-band low noise amplifier (LNA) with ultra low gain flatness for wide-band wireless multimedia and satellite communication systems. The 40-㎓-band 4-stage LNA MMIC (Monolithic Microwave Integrated Circuit) demonstrates a small signal gain of more than 20 ㏈, an input return loss of 10.3 ㏈, and an output return loss of 16.3 ㏈ for 37$\square$42 ㎓. The gain flatness of the 40-㎓-band 4-stage LNA MMIC was 0.1 ㏈ for 37$\square$42 ㎓. The noise figure of the 40 ㎓-band LNA was simulated to be less than 2.7 dB for 37~42 ㎓. The chip size of the 4-stage LNA MMIC was 3.7${\times}$1.7 $\textrm{mm}^2$.

• ETRI Journal
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• v.29 no.5
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• pp.670-672
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• 2007

An ultra-wideband low-noise amplifier is proposed with operation up to 8.2 GHz. The amplifier is fabricated with a 0.18-${\mu}m$ CMOS process and adopts a two-stage cascode architecture and a simplified Chebyshev filter for high gain, wide band, input-impedance matching, and low noise. The gain of 19.2 dB and minimum noise figure of 3.3 dB are measured over 3.4 to 8.2 GHz while consuming 17.3 mW of power. The Proposed UWB LNA achieves a measured power-gain bandwidth product of 399.4 GHz.