• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.12
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• pp.100-108
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• 2010

A low voltage wire should be used considering that a load used in the end is a low voltage. In regard to these wires, there are needs for research about the wire thickness calculation in accordance with IEC standard because the standardization process for IEC (KS standard) was completed on June 30, 2005, and they stopped producing NEC-standard products by the order from Korean Agency for Technology and Standards under Ministry of Knowledge Economy (former Ministry of Commerce, Industry and Energy) since July 1, 2006. This study compared, in terms of the thickness calculation of low voltage wire, a reduction factor application by IEC standard about allowed current and an application for calculation of voltage drop. It also proposed the formula for IEC standard to decrease errors and resolve the difficulty of standardized calculation by analyzing the difference between simplified formula and standardized formula that are the most frequently used calculation method of voltage drop.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.70-82
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• 2014

A nano-power CMOS voltage reference is proposed in this paper. Through a combination of switched-capacitor technology with the body effect in MOSFETs, the output voltage is defined as the difference between two gate-source voltages using only a single PMOS transistor operated in the subthreshold region, which has low sensitivity to the temperature and supply voltage. A low output, which breaks the threshold restriction, is produced without any subdivision of the components, and flexible trimming capability can be achieved with a composite transistor, such that the chip area is saved. The chip is implemented in $0.18{\mu}m$ standard CMOS technology. Measurements show that the output voltage is approximately 123.3 mV, the temperature coefficient is $17.6ppm/^{\circ}C$, and the line sensitivity is 0.15 %/V. When the supply voltage is 1 V, the supply current is less than 90 nA at room temperature. The area occupation is approximately $0.03mm^2$.

• Journal of Electrical Engineering and Technology
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• v.12 no.3
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• pp.1187-1194
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• 2017

In this paper, a high step-up DC-DC PWM converter with continuous input current and low voltage stress is presented for renewable energy application. The proposed converter is composed of a boost converter integrated with an auxiliary step-up circuit. The auxiliary circuit uses an additional coupled inductor and a balancing capacitor with voltage doubler and switching capacitor technique to achieve high step-up voltage gain with an appropriate switch duty cycle. The switched capacitors are charged in parallel and discharged in series by the coupled inductor, stacking on the output capacitor. In the proposed converter, the voltage stress on the main switch is clamped, so a low voltage switch with low ON resistance can be used to reduce the conduction loss which results in the efficiency improvement. A detailed discussion on the operating principle and steady-state analyses are presented in the paper. To justify the theoretical analysis, experimental results of a 200W 40/400V prototype is presented. In addition, the conducted electromagnetic emissions are measured which shows a good EMC performance.

• Journal of Power Electronics
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• v.14 no.3
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• pp.468-477
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• 2014

This study proposes an optimized design of a dual active bridge converter for a low-voltage charger in a military uninterrupted power supply (UPS) system. The dual active bridge converter is among various bi-directional DC/DC converters that possess a high-efficiency isolated bi-directional converter. In the general design, the zero-voltage switching(ZVS) region is reduced when the battery voltage is high. By contrast, efficiency is low because of high conduction losses when the battery voltage is low. Variable switching frequency is applied to increase the ZVS region and the power conversion efficiency, depending on battery voltage changes. At the same duty, the same power is obtained regardless of the battery voltage using the variable switching frequency. The proposed method is applied to a 5 kW prototype dual active bridge converter, and the experimental results are analyzed and verified.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.5
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• pp.371-378
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• 2015

In this paper, a different type of pulse width modulation (PWM) control scheme for a buck converter is introduced. The proposed buck converter uses PWM with frequency hopping and a low quiescent.current low dropout (LDO) voltage regulator with a power supply rejection ratio enhancer to reduce high spurs, harmonics and output voltage ripples. The low quiescent.current LDO voltage regulator is not described in this paper. A three-bit binary-to-thermometer decoder scheme and voltage ripple controller (VRC) is implemented to achieve low voltage ripple less than 3mV to increase the efficiency of the buck converter. An internal clock that is synchronized to the internal switching frequency is used to set the hopping rate. A center frequency of 2.5MHz was chosen because of the bluetooth low energy (BLE) application. This proposed DC-DC buck converter is available for low-current noise-sensitive loads such as BLE and radio frequency loads in portable communications devices. Thus, a high-efficiency and low-voltage ripple is required. This results in a less than 2% drop in the regulator's efficiency, and a less than 3mV voltage ripple, with -26 dBm peak spur reduction operating in the buck converter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.15-21
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• 2004

In this paper a new structure of BJT is proposed to improve the saturation voltage characteristics so that it can be used to the low power switching devices. In the case of the conventional finger transistor(FT), the saturation voltage is so high that it dose not satisfy the requirements for the low power device. So the other multi base island transistor(MBIT) is suggested and its saturation voltage is so low in the region of low current that it satisfy the requirement for the low power switching devices, but in region of the high current the saturation voltage tends to increase so that it does not satisfy the requirements for the low power switching devices. So in this paper a new structure of folded back electrode transistor(FBET) is proposed and the characteristics is investigated. When the new structure is applied the emitter area is increased by 35 % so the saturation voltage is reduced by 30 % at the low current region and the contact area is increased by 92 % so the saturation voltage is reduced by totally f % at the high current region with the reduction of 30 % by the increase of the emitter area and the reduction of 7 % by the increase of the emitter contact area.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.6
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• pp.67-74
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• 2010

Most of domestic low-voltage consumers are supplied from the TN-C system of KEPCO, but their load installations have established according to the national statutory standard for electrical installations based on the TT system. In this work, to propose the proper system earthing arrangements of ensuring the protection of information-technology equipment against lightning surges, the protection performance of TT and TN systems against lightning surges was investigated. As a result, when lightning surge was injected to the neutral line of distribution system, the potential difference between the equipment earth terminal and neutral point of low-voltage mains in a TT system was significantly raised. The TT system is not advised due to the risk of damage to the sensitive computer equipment. Main equipotential bonding is an important requirement for protection of low-voltage installations against lightning surges. The TN system provides the best means to reduce the incoming lightning surges through the neutral line of low-voltage service systems. In addition, It is highly recommended to install the additional earthing at the service position of low-voltage consumers.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.17 no.3
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• pp.119-126
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• 2003

The size of low voltage level conductor cables can be installed with a long length just like a aviation field, shall be determined for considering the ampacity of cable and the drop of voltage for the power system. Therefore, The size of the conductor cables may be larger one for considering the tolerable voltage drop comparatively, although the allowable ampacity of the conductor cables may have a margin in comparison with the rated full load current In this case, the conductor cables' allowable ampacity will be very larger than the rated full load current and the generated heat of the conductor will be relatively downed. The conductor cables' alternating current resistance corrected with the maximum allowable temperature of the conductors, has been applied on the general formula for the calculating the voltage drop in determinating the size of low voltage level conductor cables, and the resistance is larger than the resistance corrected with the actual temperature of the conductor cables. This paper was studied for the purpose of the conductor resistance corrected with the actual temperature rise of the conductor and address the economic design formula so that this studies shall minimize the errors which can be occurred in comparison with the general formula and which can be applied in design work for determining the size of low voltage level conductor cables.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.195-198
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• 2000

In this paper the insulation characteristics test results of 25 low-voltage induction motors($3\phi$, 5HP, 380V) are presented. Five different types of insulation techniques are applied to 25 motors. The maximum partial discharge (PD) magnitude ($\textrm{Q}_{m}$) discharge inception voltage (DIV) dissipation factor tip-up ($\Delta$tan$\delta$) and rate of change in AC current($\Delta$I) are measured by PD and AC current tests. Also the insulation breakdown tests by high voltage pulse are performed and the corresponding breakdown voltage are obtained.

• ETRI Journal
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• v.20 no.1
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• pp.37-45
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• 1998

Reduced surface field lateral double-diffused MOS transistor for the driving circuits of plasma display panel and field emission display in the 120V region have been integrated for the first time into a low-voltage $1.2{\mu}m$ analog CMOS process using p-type bulk silicon. This method of integration provides an excellent way of achieving both high power and low voltage functions on the same chip; it reduces the number of mask layers double-diffused MOS transistor with a drift length of $6.0{\mu}m$ and a breakdown voltage greater than 150V was self-isolated to the low voltage CMOS ICs. The measured specific on-resistance of the lateral double-diffused MOS in $4.8m{\Omega}{\cdot}cm^2$ at a gate voltage of 5V.