• International Journal of Fluid Machinery and Systems
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• v.6 no.2
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• pp.49-55
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• 2013

Water lubricated guide bearing was newly released and has been applied to actual hydro turbines with vertical shaft. As a result, they can have not only high bearing performance but environmental advantages in meeting the demand for reducing river pollution by oil leakage from oil lubricated guide bearing. The PTFE composite guide bearing was tested by experimental equipment operated under conditions similar to those of actual hydro turbines. Circumferential and axial tilting bearing segments help to improve the bearing performance and efficiency due to low friction loss in the bearing system. Furthermore, bearing cooling systems could be eliminated and maintenance periods could be extended, thus the initial investment and operating costs of the hydroelectric power plant are reduced.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.4
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• pp.1814-1821
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• 2012

As a new Korean grid code which includes LVRT requirement to wind farm of which capacity is greater than 20MW is activated in 2012, this paper developed the analytical model of the Korean LVRT for the simulation based feasibility study of the wind farm interconnection into power systems. The developed model of the LVRT is verified by applying it into the performance evaluation of the wind farm interconnected power systems and the effect of Korean LVRT is analyzed through case studies considering typical disturbances of power systems.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.59-65
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• 2013

Conventional synchronous design circuits cannot only satisfy the timing requirement of the low voltage digital systems, but also they may generate wrong outputs under the influence of PVT variations and aging effects. Therefore, in this paper, a NCL (Null Convention Logic) design as an asynchronous design method has been proposed, where the NCL method doesn't require any timing analysis, and it has a very simple design methodology. Base on the NCL method, a new low power reliable ALU has been designed and implemented using MagnaChip-SKhynix 0.18um CMOS technology. The experimental results of the proposed NCL ALU have been compared to those of a conventional pipelined ALU in terms of power consumption and speed.

• IEIE Transactions on Smart Processing and Computing
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• v.2 no.4
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• pp.248-254
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• 2013

The size and power consumption of digital circuits including the dimming circuit part will increase for high-performance solid state lighting (SSL) systems in the future. This study examined the low-power consumption of adiabatic dynamic CMOS logic (ADCL) due to the principles of adiabatic charging. Furthermore, the designed low-power ADCL digital pulse width modulation (PWM) was optimized for SSL dimming systems. For this purpose, an ADCL digital 3-bit PWM was optimized in two steps. In the first step, the architecture of the ADCL digital 3-bit PWM was miniaturized. In the second step, the clock cut-off circuit was designed and added to the ADCL PWM. As a result, compared to the original configuration, 60 transistors and 15 capacitors of ADCL digital 3-bit PWM were reduced for miniaturization. Moreover, the clock cut-off circuit, which controls wake-up and sleep mode of ADCL D-FFs, was designed. The power consumption of an optimized ADCL digital PWM for all bit patterns decreased by 54 %.

• Journal of Electrical Engineering and Technology
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• v.12 no.2
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• pp.726-737
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• 2017

The use of energy storage systems (ESSs) has become a feasible solution to solve the wind power intermittency issue. However, the use of ESSs increases the system cost significantly. In this paper, an optimal power flow control scheme to minimize the ESS capacity is proposed by using the zero-phase delay low-pass filter which can eliminate the phase delay between the dispatch power and the wind power. In addition, the filter time constant is optimized at the beginning of each dispatching interval to ensure the fluctuation mitigation requirement imposed by the grid code with a minimal ESS capacity. And also, a short-term power dispatch control algorithm is developed suitable for the proposed power dispatch based on the zero-phase delay low-pass filter with the predetermined ESS capacity. In order to verify the effectiveness of the proposed power management approach, case studies are carried out by using a 3-MW wind turbine with real wind speed data measured on Jeju Island.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.165-175
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• 2010

This paper presents a fine-grain supply-voltage-control scheme for low-power FPGAs. The proposed supply-voltage-control scheme detects the critical path in real time with small overheads by exploiting features of asynchronous architectures. In an FPGA based on the proposed supply-voltage-control scheme, logic blocks on the sub-critical path are autonomously switched to a lower supply voltage to reduce the power consumption without system performance degradation. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a look-up-table without level shifters is employed. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block. The proposed FPGA is fabricated using the e-Shuttle 65 nm CMOS process. Correct operation of the proposed FPGA on the test chip is confirmed.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.31-34
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• 2004

In wireless communication systems, low-power metrics is becoming a burdensome problem in the portable terminal design, because of portability constraints. This paper presents design architecture of a low-power partial correlation Digital Matched Filter for the IMT-2000 communication systems. The proposed approach focuses on efficient circuit size, power dissipation, maintaining the operating throughput. The proposed architecture was verified by using Xilinx FPGA.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.4 no.1
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• pp.79-83
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• 2004

This paper presents the performance analysis for CPL based design of a Low power digital neuroprocessor. We have verified the functionality of the components at the high level using Verilog and carried out the simulations in Silos. The components of the proposed digital neuroprocessor have also been verified at the layout level in LASI. The layouts have then been simulated and analyzed in Winspice for their timing characteristics. The result shows that the proposed digital neuroprocessor consistently consumes less power than other designs of the same function. It can also be seen that the proposed functions have lesser propagation delay and thus higher speed compared to the other designs.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.2089-2091
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• 2000

Pulsed power systems consist of a capacitor bank, an isolated high-voltage charging power-supply, high-current bus-work for charging and discharging and a control system. In such pulsed power systems, the operating-lifetime of the capacitors is closely dependent on the voltage reversal. Hence, most capacitor-discharging systems includes crowbar circuits. The crowbar circuit prevents the capacitor recharging with reverse voltage. Usually it consists of crowbar resistors and high pulse-current diode-stacks connected in series. The requirements for the diode-stacks are fast-recovery time and high-voltage and large-current ratings, which results in the high cost of the pulsed-power system. This paper presents a protection scheme of a charging and discharging system of a 500kJ capacitor bank using a low-cost crowbar circuit and safety-fuses.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.487-488
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• 2015

New inverter motor drive systems consume 30%~50% less energy compared to existing motor drive systems. For inverter motor drive systems, the development of a 1200V high side driver is critical. This paper presents an advanced 1200V high side driver with low power consumption and high ruggedness. This solution implements a high voltage level shifter which consumes low power by adding a clamped VGS LDMOS driver to the conventional short pulse generator. Moreover, this paper proposes a highly rugged 1200V LDMOS which improves SOA by limiting the hole current. This paper could be applied to smart power modules used for HVAC (heating, ventilation, and airconditioning) and industrial inverters. Consequently, this paper will provide design engineers with an understanding of how they can make a significant contribution to worldwide energy savings.