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http://dx.doi.org/10.5573/JSTS.2010.10.3.165

Evaluation of a Self-Adaptive Voltage Control Scheme for Low-Power FPGAs  

Ishihara, Shota (Intelligent Integrated Systems Laboratory, Graduate School of Information Science, TOHOKU University)
Xia, Zhengfan (Intelligent Integrated Systems Laboratory, Graduate School of Information Science, TOHOKU University)
Hariyama, Masanori (Intelligent Integrated Systems Laboratory, Graduate School of Information Science, TOHOKU University)
Kameyama, Michitaka (Intelligent Integrated Systems Laboratory, Graduate School of Information Science, TOHOKU University)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.10, no.3, 2010 , pp. 165-175 More about this Journal
Abstract
This paper presents a fine-grain supply-voltage-control scheme for low-power FPGAs. The proposed supply-voltage-control scheme detects the critical path in real time with small overheads by exploiting features of asynchronous architectures. In an FPGA based on the proposed supply-voltage-control scheme, logic blocks on the sub-critical path are autonomously switched to a lower supply voltage to reduce the power consumption without system performance degradation. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a look-up-table without level shifters is employed. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block. The proposed FPGA is fabricated using the e-Shuttle 65 nm CMOS process. Correct operation of the proposed FPGA on the test chip is confirmed.
Keywords
Reconfigurable VLSI; multiple supply voltages; dynamic voltage and frequency scaling; asynchronous architecture;
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1 M. Hariyama, S. Ishihara, and M. Kameyama, “Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture,” IEICE Trans. Electron, Vol. E91-C, No.9, pp.1419-1426, 2008.   DOI
2 S. Ishihara, Y. Komatsu, M. Hariyama, and M. Kameyama, “An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters,” in Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2009, pp.145-150.
3 J. Sparsø and S. Furber, Principles of Asynchronous Circuit Design: A Systems Perspective. Kluwer Academic Publishers, 2001.
4 T. Kuroda and M. Hamada, “Low-Power CMOS Digital Design with Dual Embedded Adaptive Power Supplies,” IEEE Journal of Solid-State Circuits, Vol.35, No.4, pp.652-655, 2000.   DOI   ScienceOn
5 Gated clock conversion with Synplicity’s synthesis products, Synplicity Inc. Application Note, Jul., 2003.
6 Synthesis and Simulation Design Guide, Xilinx Inc., 2008.
7 W. Chong, M. Hariyama, and M. Kameyama, “Low-Power Field-Programmable VLSI Using Multiple Supply Voltages,” IEICE transactions on fundamentals of electronics, communications and computer sciences, Vol.88, No.12, pp.3298-3305, 2005.
8 S. Ishihara, Z. Xia, M. Hariyama, and M. Kameyama, “Architecture of a Low-Power FPGA Based on Self-Adaptive Voltage Control,” in Proc. International SoC Design Conference (ISOCC), 2009, pp.274-277.
9 M. Hariyama, S. Ishihara, , and M. Kameyama, “A Low-Power Field-Programmable VLSI Based on a Fine-Grained Power-Gating Scheme,” in Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug., 2008, pp.430-433.
10 S. Ishihara, M. Hariyama, and M. Kameyama, “A Low-Power FPGA Based on Autonomous Fine-Grain Power-Gating,” in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), Jan., 2009, pp.119-120.
11 K. Maheswaran and V. Akella, “PGA-STC: programmable gate array for implementing selftimed circuits,” International Journal of Electronics, Vol.84, No.3, pp.255-267, 1998.   DOI
12 R. Payne, “Asynchronous FPGA Architectures,” IEE Computers and Digital Techniques, Vol.143, No.5, 1996.
13 J. Teifel and R. Manohar, “An asynchronous dataflow FPGA architecture,” IEEE Transactions on Computers, Vol.53, No.11, pp.1376-1392, 2004.   DOI   ScienceOn
14 V. Kursun and E. G. Friedman, Multi-voltage CMOS Circuit Design. Wiley, 2006.
15 M. Hariyama, S. Ishihara, C. C. Wei, and M. Kameyama, “A Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture,” in Proceedings of the IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov., 2007, pp.380-383.
16 M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual: For System-on-Chip Design. Springer, 2007.
17 G. Magklis, G. Semeraro, D. H. Albonesi, S. G. Dropsho, S. Dwarkadas, and M. L. Scott, “Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor,” IEEE Micor, Vol.23, No.6, pp.62-68, 2003.   DOI   ScienceOn
18 G. Semeraro, G. Magklis, R. Balasubramonian, D. H. Albonesi, S. Dwarkadas, and M. L. Scott, “Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling,” in Proc. International Symposium on High-Performance Computer Architecture, 2002, pp.29-40.