International Journal of Fuzzy Logic and Intelligent Systems

  • 제4권1호
  • /
  • Pages.79-83
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  • 2004
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  • 1598-2645(pISSN)
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  • 2093-744X(eISSN)
한국지능시스템학회 (Korean Institute of Intelligent Systems)
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Low Power Design of the Neuroprocessor

  • Pandya, A.S. (Dept. of Computer Science ＆ Engineering, Florida Atlantic University, Div of Information and Computer Engineering) ;
  • Agarwal, Ankur (Dept. of Computer Science ＆ Engineering, Florida Atlantic University) ;
  • Chae, G.Y. (IT Design Research Center Silla University)
  • 발행 : 2004.06.01
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초록

This paper presents the performance analysis for CPL based design of a Low power digital neuroprocessor. We have verified the functionality of the components at the high level using Verilog and carried out the simulations in Silos. The components of the proposed digital neuroprocessor have also been verified at the layout level in LASI. The layouts have then been simulated and analyzed in Winspice for their timing characteristics. The result shows that the proposed digital neuroprocessor consistently consumes less power than other designs of the same function. It can also be seen that the proposed functions have lesser propagation delay and thus higher speed compared to the other designs.

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참고문헌

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