JSTS:Journal of Semiconductor Technology and Science

  • 제10권3호
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  • Pages.165-175
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  • 2010
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Evaluation of a Self-Adaptive Voltage Control Scheme for Low-Power FPGAs

  • Ishihara, Shota (Intelligent Integrated Systems Laboratory, Graduate School of Information Science, TOHOKU University) ;
  • Xia, Zhengfan (Intelligent Integrated Systems Laboratory, Graduate School of Information Science, TOHOKU University) ;
  • Hariyama, Masanori (Intelligent Integrated Systems Laboratory, Graduate School of Information Science, TOHOKU University) ;
  • Kameyama, Michitaka (Intelligent Integrated Systems Laboratory, Graduate School of Information Science, TOHOKU University)
  • 투고 : 2010.06.28
  • 심사 : 2010.08.25
  • 발행 : 2010.09.30
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초록

This paper presents a fine-grain supply-voltage-control scheme for low-power FPGAs. The proposed supply-voltage-control scheme detects the critical path in real time with small overheads by exploiting features of asynchronous architectures. In an FPGA based on the proposed supply-voltage-control scheme, logic blocks on the sub-critical path are autonomously switched to a lower supply voltage to reduce the power consumption without system performance degradation. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a look-up-table without level shifters is employed. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block. The proposed FPGA is fabricated using the e-Shuttle 65 nm CMOS process. Correct operation of the proposed FPGA on the test chip is confirmed.

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참고문헌

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피인용 문헌

  1. Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates vol.E95.C, pp.8, 2012, https://doi.org/10.1587/transele.E95.C.1434
  2. Adaptive Voltage Scaling with In-Situ Detectors in Commercial FPGAs vol.64, pp.1, 2015, https://doi.org/10.1109/TC.2014.2365963