• Title/Summary/Keyword: Low-Power Device

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Ultra-Low Powered CNT Synaptic Transistor Utilizing Double PI:PCBM Dielectric Layers (더블 PI:PCBM 유전체 층 기반의 초 저전력 CNT 시냅틱 트랜지스터)

  • Kim, Yonghun;Cho, Byungjin
    • Korean Journal of Materials Research
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    • v.27 no.11
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    • pp.590-596
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    • 2017
  • We demonstrated a CNT synaptic transistor by integrating 6,6-phenyl-C61 butyric acid methyl ester(PCBM) molecules as charge storage molecules in a polyimide(PI) dielectric layer with carbon nanotubes(CNTs) for the transistor channel. Specifically, we fabricated and compared three different kinds of CNT-based synaptic transistors: a control device with $Al_2O_3/PI$, a single PCBM device with $Al_2O_3/PI:PCBM$(0.1 wt%), and a double PCBM device with $Al_2O_3/PI:PCBM$(0.1 wt%)/PI:PCBM(0.05 wt%). Statistically, essential device parameters such as Off and On currents, On/Off ratio, device yield, and long-term retention stability for the three kinds of transistor devices were extracted and compared. Notably, the double PCBM device exhibited the most excellent memory transistor behavior. Pulse response properties with postsynaptic dynamic current were also evaluated. Among all of the testing devices, double PCBM device consumed such low power for stand-by and its peak current ratio was so large that the postsynaptic current was also reliably and repeatedly generated. Postsynaptic hole currents through the CNT channel can be generated by electrons trapped in the PCBM molecules and last for a relatively short time(~ hundreds of msec). Under one certain testing configuration, the electrons trapped in the PCBM can also be preserved in a nonvolatile manner for a long-term period. Its integrated platform with extremely low stand-by power should pave a promising road toward next-generation neuromorphic systems, which would emulate the brain power of 20 W.

A study on the development of a virtual power plant platform for the Efficient operation of small distributed resources (소규모 분산자원의 효율적 운용을 위한 가상발전소 플랫폼 개발)

  • Kim, Hee-Chul;Hong, Ho-Pyo
    • Journal of Digital Convergence
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    • v.19 no.11
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    • pp.365-371
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    • 2021
  • In this study, The Virtual Power Plant (VPP) solution platform considered in this study minimizes the cost and investment risk associated with the construction of power generation and transmission facilities. In addition, it includes a Demand Response (DR) program operation function to meet consumers' electricity demand. With the introduction of VPP, it is possible to provide more eco-friendly and efficient power by responding to changes in consumer load in real time through existing generators and DR programs without large-scale facility investment in power generation and transmission/distribution sectors. In order to link the communication device to the solar power and ESS linkage device, it is necessary to transmit data in the control/state between the device device and the edge system and develop an IoT device and interworking platform (OneM2M).

Analytical Model of Double Gate MOSFET for High Sensitivity Low Power Photosensor

  • Gautam, Rajni;Saxena, Manoj;Gupta, R.S.;Gupta, Mridula
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.5
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    • pp.500-510
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    • 2013
  • In this paper, a high-sensitivity low power photodetector using double gate (DG) MOSFET is proposed for the first time using change in subthreshold current under illumination as the sensitivity parameter. An analytical model for optically controlled double gate (DG) MOSFET under illumination is developed to demonstrate that it can be used as high sensitivity photodetector and simulation results are used to validate the analytical results. Sensitivity of the device is compared with conventional bulk MOSFET and results show that DG MOSFET has higher sensitivity over bulk MOSFET due to much lower dark current obtained in DG MOSFET because of its effective gate control. Impact of the silicon film thickness and gate stack engineering is also studied on sensitivity.

Design and Implementation of Low-Power Object-based IP Storage for Mobile Devices using WLAN Power Control (WLAN 전력제어를 적용한 모바일 단말용 저전력 객체기반 IP 스토리지 설계 및 구현)

  • Nam, Young-Jin;Choi, Min-Seok;Jeon, Young-Joon;Ryu, Jeong-Tak;Moon, Byung-Hyun
    • Journal of Korea Society of Industrial Information Systems
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    • v.12 no.4
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    • pp.32-40
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    • 2007
  • A mobile device accesses large-sized data in object-based IP storage as an object unit over IP network. It relies heavily on a WLAN device, which has been known as one of the major power consumers. This paper designs and implements low-power object-based IP storage for mobile devices using an efficient WLAN power control. The proposed WLAN power control exploits prefetch buffer to maximize the idleness for incoming network traffic and controls available WLAN power modes to minimize the power consumption. Our experimental results reveal that the proposed WLAN control can save the total power consumption in a PXA270-based mobile device about 9% while playing the multimedia contents through an object-based IP storage device

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A Cleaning Policy for Mobile Computers using Flash Memory (플래시메모리를 사용하는 이동컴퓨터에서 클리닝 정책)

  • 민용기;박승규
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.495-498
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    • 1998
  • Mobile computers have restrictions for size, weight, and power consumption that are different from traditional workstations. Storage device must be smaller, lighter. Low power consumed storage devices are needed. At the present time, flash memory device is a reasonable candidate for such device. But flash memory has drawbacks such as bulk erase operation and slow program time. This causes of worse average write performances. This paper suggests a storage method which improves write performance.

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Optimal Design of GaN Power MOSFET Using Al2O3 Gate Oxide (Al2O3 게이트 절연막을 이용한 GaN Power MOSFET의 설계에 관한 연구)

  • Nam, Tae-Jin;Chung, Hun-Suk;Kang, Ey-Goo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.24 no.9
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    • pp.713-717
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    • 2011
  • This paper was carried out design of 600 V GaN power MOSFET Modeling. We decided trench gate type one for design. we carried out device and process simulation with T-CAD tools. and then, we have extracted optimal device and process parameters for fabrication. we have analysis electrical characteristics after simulations. As results, we obtained 600 V breankdown voltage and $0.4\;m{\Omega}cm^2ultra$ low on resistance. At the same time, we carried out field ring simulation for obtaining high voltage.

Design of a Low Power Self-tuning Digital System Considering Aging Effects (노화효과를 고려한 저전력 셀프 튜닝 디지털 시스템의 설계)

  • Lee, Jin-Kyung;Kim, Kyung Ki
    • IEMEK Journal of Embedded Systems and Applications
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    • v.13 no.3
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    • pp.143-149
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    • 2018
  • It has become ever harder to design reliable circuits with each nanometer technology node; under normal operation conditions, a transistor device can be affected by various aging effects resulting in performance degradation and eventually design failure. The reliability (aging) effect has traditionally been the area of process engineers. However, in the future, even the smallest of variations can slow down a transistor's switching speed, and an aging device may not perform adequately at a very low voltage. Therefore, circuit designers need to consider these reliability effects in the early stages of design to make sure there are enough margins for circuits to function correctly over their entire lifetime. However, such an approach excessively increases the size and power dissipation of a system. As the impact of reliability, new techniques in designing aging-resilient circuits are necessary to reduce the impact of the aging stresses on performance, power, and yield or to predict the failure of a system. Therefore, in this paper, a novel low power on-chip self-tuning circuit considering the aging effects has been proposed.

A Design of BJT-based ESD Protection Device combining SCR for High Voltage Power Clamps

  • Jung, Jin-Woo;Koo, Yong-Seo
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.3
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    • pp.339-344
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    • 2014
  • This paper presents a novel bipolar junction transistor (BJT) based electrostatic discharge (ESD) protection device. This protection device was designed for 20V power clamps and fabricated by a process with Bipolar-CMOS-DMOS (BCD) $0.18{\mu}m$. The current-voltage characteristics of this protection device was verified by the transmission line pulse (TLP) system and the DC BV characteristic was verified by using a semiconductor parameter analyzer. From the experimental results, the proposed device has a trigger voltage of 29.1V, holding voltage of 22.4V and low on-resistance of approximately $1.6{\Omega}$. In addition, the test of ESD robustness showed that the ESD successfully passed through human body model (HBM) 8kV. In this paper, the operational mechanism of this protection device was investigated by structural analysis of the proposed device. In addition, the proposed device were obtained as stack structures and verified.

A Study on Improvement of Low-power Memory Architecture in IoT/edge Computing (IoT/에지 컴퓨팅에서 저전력 메모리 아키텍처의 개선 연구)

  • Cho, Doosan
    • Journal of the Korean Society of Industry Convergence
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    • v.24 no.1
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    • pp.69-77
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    • 2021
  • The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.

Micro Power Properties of Harvesting Devices as a Function of PZT cantilever length and gross area (PZT 캔틸레버의 길이와 면적에 따른 에너지 하베스팅 장치의 출력 특성)

  • Kim, I.S.;Joo, H.K.;Song, J.S.;Kim, M.S.;Jeong, S.J.;Lee, D.S.
    • Proceedings of the KIEE Conference
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    • 2008.07a
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    • pp.1246-1247
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    • 2008
  • With recent advanced in portable electric devices, wireless sensor, MEMS and bio-Mechanics device, the new typed power supply, not conventional battery but self-powered energy source is needed. Particularly, the system that harvests from their environments are interests for use in self powered devices. For very low powered devices, environmental energy may be enough to use power source. Therefore, in other to made piezoelectric energy harvesting device, PMN-PZT thick film was formed by the screen printing method on the Ag/Pd coated alumina substrate. The layer was 8 layers and slurry where a-terpineol, ethycellulose, ferro B-75001 as Vehicle, PMN-PZT powder used are fabricated by ball mill. The output power quality was be also investigated by changing the load resistance, weight and frequency. The made piezoelectric energy harvesting device was resulted from the conditions of 33$k{\Omega}$, 0.25g, 197Hz respectively. The thick film was prepared at the condition of 2.75Vrms, and its power was 230${\mu} W$ and its thickness was 56${mu}m$. The piezoelectric energy harvesting device output voltage was increased, when the load weight, load resistance was increasing and resonance frequency was diminishing. The other side, resonance frequency was diminished, when the weight was increasing. And output power was continuously it changed by load resistance, output voltage, weight and resonance frequency.

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