1 |
B. Paul, K. Kang, H. Kufluoglu, M. A. Alam, K. Roy, "Temporal Performance Degradation Under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits," Proceedings of Design, Automation and Test in Europe, Vol. 1, pp. 1-6, 2006.
|
2 |
H. Mostafa, M. Anis, M. Elmasry, "NBTI and Process Variations Compensation Circuits Using Adaptive Body Bias," IEEE transactions on semiconductor manufacturing, Vol. 25, No. 3, pp .460-467, 2012.
DOI
|
3 |
Z. Gan, W. Wong, J. J. Liou, "Semiconductor Process Reliability in Practice," McGraw Hill, 2013.
|
4 |
M. Agarwal, B. Paul, M. Zhang, S. Mitra, "Circuit Failure Prediction and Its Application to Transistor Aging," Proceedings of IEEE VLSI test symposium, pp. 277-286, 2007.
|
5 |
K. K. Kim, H. Nan, K. Choi, "Power Gating for Ultra-low Voltage Nanometer ICs," Proceedings of IEEE International Circuits and Systems, pp. 1472-1475, 2010.
|