• Journal of the Korean Society for Heat Treatment
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• v.28 no.3
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• pp.134-138
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• 2015

Ag intermediated $TiO_2$ films were deposited by RF and DC magnetron sputtering and then vacuum annealed at 100, 200 and $300^{\circ}C$ for 30 minutes to investigate the effect of annealing temperature on the structural and optical properties of the films. For all depositions, the thickness of the $TiO_2$ and Ag films were kept constant at 24 and 15 nm by controlling the deposition time. As-deposited $TiO_2/Ag/TiO_2$ trilayer films have a weak crystalline and an optical reflectance in a near infrared wavelength region of 77.8%, while the films annealed at $300^{\circ}C$ show the polycrystalline structure and an increased mean optical reflectance of 80.4%. From the experimental results, it can be concluded that increasing the annealing temperature enhanced the structural and optical properties of the $TiO_2/Ag/TiO_2$ films.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.687-694
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• 2008

This paper is focused on the improvement of MOS device reliability related to deuterium process. The injection of deuterium into the gate oxide film was achieved through two kind of method, high-pressure annealing and low-energy implantation at the back-end of line, for the purpose of the passivation of dangling bonds at $SiO_2/Si$ interface. Experimental results are presented for the degradation of 3-nm-thick gate oxide ($SiO_2$) under both negative-bias temperature instability (NBTI) and hot-carrier injection (HCI) stresses using P and NMOSFETs. Annealing process was rather difficult to control the concentration of deuterium. Because when the concentration of deuterium is redundant in gate oxide excess traps are generated and degrades the performance, we found annealing process did not show the improved characteristics in device reliability, compared to conventional process. However, deuterium ion implantation at the back-end process was effective method for the fabrication of the deuterated gate oxide. Device parameter variations under the electrical stresses depend on the deuterium concentration and are improved by low-energy deuterium implantation, compared to conventional process. Our result suggests the novel method to incorporate deuterium in the MOS structure for the reliability.

• Journal of Korean Vacuum Science & Technology
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• v.2 no.2
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• pp.97-100
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• 1998

We have investigated the effects of crystalline activation on solid phase crystallization (SPC) of amorphous silicon (a-Si) thin films. Wet blasting and self ion implantation were employed as the activation treatments to induce macro or micro crystalline damages on deposited a-Si films. Low temperature and larger grain crystallization were obtained by the applied two-step activation. High degree of crystallinity was also observed on both furnace and rapid SPC. crystalline activations showed the promotion of nucleation on the activated regions and the retardation of growth in an amorphous matrix in SPC. The observed behavior of two-step SPC was strongly dependent on the applied activation and annealing processes. It was also found that the diversified effects by macro and micro activations on the SPC were virtually diminished as the annealing temperature increased.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.4
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• pp.342-349
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• 2009

This study investigated the growth characteristics of carbon nanotubes (CNTs) by changing a period of annealing time and a $C_{2}H_{2}/H_2$ flow ratio at temperature as low as $450^{\circ}C$ with inductively coupled plasma chemical vapor deposition. The 1-nm-thick Fe-Ni-Co alloy thin film served as a catalyst layer for the growth of CNTs, which was thermally evaporated on the 15-nm-thick Al underlayer deposited on the 50-nm-thick Ti diffusion barrier. The annealing at low temperature of $450^{\circ}C$ brought about almost no granulation of the catalyst layer, and the CNT growth was not affected by a period of annealing time. A study of changing the flow rate of $C_{2}H_{2}$ and $H_2$ showed that as the ratio of the $C_{2}H_{2}$ flow rate to the $H_2$ flow rate was lowered, the CNTs were grown to be longer With further decreasing the flow ratio, the length of CNTs reached the maximum and then became shorter. Under the optimized gas flow rates, we successfully synthesized CNTs with a uniform length over a 4-inch Si wafer at $450^{\circ}C$.

• Journal of the Korean Magnetics Society
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• v.3 no.4
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• pp.305-309
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• 1993

Thermal stability of Co/Cu artificial superlattice (AS) prepared by RF-magnetron sputtering and the effect of low temperature annealing on the magnetoresistance of the AS have been investigated in this work. Dependence of annealing behavior on the Cu spacer thickness, Fe underlayer thickness, and kind of the underlayer was examined and the relationship between the interfacial reaction and magnetoresistance was studied. It turned out that when Co/Cu AS was annealed at low temperature ($<450^{\circ}C$), the magnetoresistance could increase in the case of AS with thick spacer Cu ($20~25\AA$) layer, whereas it decreased in the case of AS with thin spacer Cu ($7\AA$) layer, which of the former is in contrast with previous reports and the latter in consistent with them. The increase of magnetoresistance is due to increase of interfacial atomic sharpness, which is supported by low angle X-ray diffraction analysis. The thermal stability of Co/Cu AS was better in the case of thick Fe underlayered AS. Interfacial reaction (separation of intermixed Co and Cu) could be observed at lower temperature for (200)-textured samples than for (111)-textured samples, which can be interpreted in terms of interdiffusion kinetics depending on the crystallographic orientation.

• Korean Journal of Materials Research
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• v.9 no.5
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• pp.509-514
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• 1999

Interest in the integrated capacitors, which make it possible to reduce the size of and to obtain improved electrical performance of an electronic system, is expanding. In this study, $Ta_2$O\ulcorner thin film capacitors for MCM integrated capacitors were fabricated on a Upilex-S polymer film by DC magnetron reactive sputtering and the effects of low temperature annealing at various atmospheres and substrate surface morphology on the capacitor characteristics were discussed. The low temperature($150^{\circ}C$) annealing produced improved capacitor yield irrespective of the annealing at mosphere. But the leakage current of the $O_2$-annealed film was larger than that of any other films. This is presumably mosphere. But the leakage current of the $O_2$-annealed film was larger than that of any other films. This is presumably due to the change of the $Ta_2$O\ulcorner film surface by oxygen, which was explained by conduction mechanism study. Leakage current and breakdown field strength of the capacitors fabricated on the Upilex-S film were 7.27$\times$10\ulcornerA/$\textrm{cm}^2$ and 1.0 MV/cm respectively. These capacitor characteristics were inferior to those of the capacitors fabricated on the Si substrate but enough to be used for decoupling capacitors in multilayer package. Roughness Analysis of each layer by AFM demonstrated that the properties of the capacitors fabricated on the polymer film were affected by the surface morphology of the substrate. This substrate effect could be classified into two factors. One is the surface morphology of the polymer film and the other is the surface morphology of the metal bottom electrode determined by the deposition process. Therefore, the control of the two factors is important to obtain improved electrical of capacitors deposited on a polymer film.

• Korean Journal of Metals and Materials
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• v.48 no.2
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• pp.133-140
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• 2010

10 nm thick Ni layers were deposited on 200 nm $SiO_2/Si$ substrates using an e-beam evaporator. Then, 60 nm or 20 nm thick ${\alpha}$-Si:H layers were grown at low temperature (<$200^{\circ}C$) by a Catalytic-CVD. NiSi layers were already formed instantaneously during Cat-CVD process regardless of the thickness of the $\alpha$-Si. The resulting changes in sheet resistance, microstructure, phase, chemical composition, and surface roughness with the additional rapid thermal annealing up to $500^{\circ}C$ were examined using a four point probe, HRXRD, FE-SEM, TEM, AES, and SPM, respectively. The sheet resistance of the NiSi layer was 12${\Omega}$/□ regardless of the thickness of the ${\alpha}$-Si and kept stable even after the additional annealing process. The thickness of the NiSi layer was 30 nm with excellent uniformity and the surface roughness was maintained under 2 nm after the annealing. Accordingly, our result implies that the low temperature Cat-CVD process with proposed films stack sequence may have more advantages than the conventional CVD process for nano scale NiSi applications.

• Proceedings of the Korean Magnestics Society Conference
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• 1993.11a
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• pp.104-105
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• 1993

• Journal of the Korean Society for Heat Treatment
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• v.35 no.4
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• pp.211-219
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• 2022

It is known that superplastic materials with ultrafine grains have high elongation mainly due to grain boundary sliding. Therefore, in the present study we examined the influence of grain refinement, caused by a repetitive cold rolling and annealing process, on both superplastic elongation and superplastic deformation mechanism. The cold rolling and annealing process was repetitively applied up to 4 times using Fe-10Mn-3.5Si alloy. High-temperature tensile tests were conducted at 763 K with an initial strain rate of 1 × 10^-3 s^-1 using the specimens. The superplastic elongation increased with the number of the repetitive cold rolling and annealing process; in particular, the 4 cycled specimen exhibited the highest elongation of 372%. The primary deformation mechanism of all specimens was grain boundary sliding between recrystallized α-ferrite and reverted γ-austenite grains. The main reason for the increase in elongation with the number of the repetitive cold rolling and annealing process was the increase in fractions of fine recrystallized α-ferrite and reverted γ-austenite grains, which undergo grain boundary sliding.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.3
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• pp.227-231
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• 2008

In this study, in order to improve the electrical properties of low temperature sintering piezoelectric ceramics, $[0.05Pb(Zn_{1/2}W_{1/2})-0.07Pb(Mn_{1/3}Nb_{2/3})-0.088Pb(Zr_{0.48}Ti_{0.52})]O_3$(abbreviated as PZW-PMN-PZT) ceramic systems were fabricated using $Bi_2O_3$, CuO and $Li_2CO_3$ as sintering aids and then their piezoelectric and dielectric properties were investigated according to the amount of $Li_2CO_3$ and post-annealing process. Post-annealing process enhanced all physical properties except for mechanical quality factor (Qm). 0.2 wt% $Li_2CO_3$ added and post-annealed specimen showed the excellent values suitable for low loss piezoelectric actuator application as follow: the density = 7.86 $g/cm^3$ electromechanical coupling factor (kp) = 0.575, piezoelectric constant $d_{33}$ = 370 pC/N, dielectric constant ($\varepsilon_r$) = 1546, and mechanical quality factor (Qm) = 1161, respectively.