DOI QR코드

DOI QR Code

Property of Nano-thickness Nickel Silicides with Low Temperature Catalytic CVD

Catalytic CVD 저온공정으로 제조된 나노급 니켈실리사이드의 물성

  • Choi, Yongyoon (Department of Materials Science and Engineering, University of Seoul) ;
  • Kim, Kunil (Department of Materials Science and Engineering, University of Seoul) ;
  • Park, Jongsung (Department of Materials Science and Engineering, University of Seoul) ;
  • Song, Ohsung (Department of Materials Science and Engineering, University of Seoul)
  • 최용윤 (서울시립대학교 신소재공학과) ;
  • 김건일 (서울시립대학교 신소재공학과) ;
  • 박종성 (서울시립대학교 신소재공학과) ;
  • 송오성 (서울시립대학교 신소재공학과)
  • Received : 2009.09.15
  • Published : 2010.02.20

Abstract

10 nm thick Ni layers were deposited on 200 nm $SiO_2/Si$ substrates using an e-beam evaporator. Then, 60 nm or 20 nm thick ${\alpha}$-Si:H layers were grown at low temperature (<$200^{\circ}C$) by a Catalytic-CVD. NiSi layers were already formed instantaneously during Cat-CVD process regardless of the thickness of the $\alpha$-Si. The resulting changes in sheet resistance, microstructure, phase, chemical composition, and surface roughness with the additional rapid thermal annealing up to $500^{\circ}C$ were examined using a four point probe, HRXRD, FE-SEM, TEM, AES, and SPM, respectively. The sheet resistance of the NiSi layer was 12${\Omega}$/□ regardless of the thickness of the ${\alpha}$-Si and kept stable even after the additional annealing process. The thickness of the NiSi layer was 30 nm with excellent uniformity and the surface roughness was maintained under 2 nm after the annealing. Accordingly, our result implies that the low temperature Cat-CVD process with proposed films stack sequence may have more advantages than the conventional CVD process for nano scale NiSi applications.

Keywords

Acknowledgement

Supported by : 한국과학재단

References

  1. J. P. Gambino and E. G. Colgan, Mater. Chem. Phys. 52, 99 (1998) https://doi.org/10.1016/S0254-0584(98)80014-X
  2. E. G. Colgan, J. P. Gambino, and Q. Z. Hong, Mater. Sci. Engin. 16, 43 (1996) https://doi.org/10.1016/0927-796X(95)00186-7
  3. C. Lavoie, F. M. d'Heurle, C. Detavernier, and C. Cabral, J. Microelectronic Engin. 70, 144 (2003) https://doi.org/10.1016/S0167-9317(03)00380-0
  4. M. C. Poon, C. H. Ho, F. Deng, S. S. Lau, and H. Wong, Microelectronics Reliability 38, 1495 (1998) https://doi.org/10.1016/S0026-2714(98)00045-6
  5. J. J. Jeong, J. Lim, and C. Lee, Coatings Technology 171, 6 (2003) https://doi.org/10.1016/S0257-8972(03)00227-5
  6. S. P. Murarka, Silicide for VLSI Applications, p. 90, Academic Press (1983)
  7. Y. Y. Choi, J. S. Park, and O. S. Song, J. Kor. Inst. Met. & Mater 47, 322 (2009)
  8. S. Yamazaki, Japanese Patent 686, 435, Appl., No. S43-41742 (1968)
  9. S. Yamazaki, K. Wada, and I. Taniguchi, Jpn. J. Appl. Phys. 9 (1970)
  10. H. Matsumura, Jpn. J. Appl. Phys. 25, L949 (1986) https://doi.org/10.1143/JJAP.25.L949
  11. A. G. Sault and D. W. Goodman, Surf. Sci. 235, 28 (1990) https://doi.org/10.1016/0039-6028(90)90103-F
  12. B. P. Nelson, E. Iwaniczko, A. H. Mahan, Q. Wang, Y. Xu, R. S. Crandall, and H. M. Branz, Thin Solid Films 395, 292 (2001) https://doi.org/10.1016/S0040-6090(01)01274-3
  13. M. Karasawa, M. Sakai, K. Ishibashi, M. Tanaka, A. Masuda, and H. Matsumura, Proc. 21st Int. Display Research Conf. in Conjunction with 8th Int. Display Workshops, p. 1735, Nagoya (2001)
  14. A. Izumi and H. Matsumura, Jpn. J. Appl. Phys. 41 (2002)
  15. Crandall, H. M. Branz, Thin Solid Films 395, 292 (2001) https://doi.org/10.1016/S0040-6090(01)01274-3
  16. N. Ibaraki, Mar. Res. Soc. Proce. 345, 3 (1994) https://doi.org/10.1557/PROC-345-3
  17. Paul A. Flimm, Donald S. Garder, and William D. Nix, IEEE Trans. elec. dev. ED34, 689 (1987)