• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.2
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• pp.39-46
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• 2012

The newly designed sense amplifier in this paper has rail-to-rail input range achieving low power consumption. Reducing static power consumption generated due to DC path to ground is key element for low power consumption in this paper. The proposed sense amplifier performs power-saving operation using negative feedback circuit that controls the current flow with the newly added PMOS input terminal. As a simulation result, the proposed sense amplifier consumed about over 50 % efficiency of the average power consumed by the typical Rail-to-Rail sense amplifier.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.583-584
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• 2008

This paper presents a low-power and high-speed pulsed flip-flop based on dual-precharging and conditional discharging. The dual-precharging operation minimizes the parasitic capacitance of each precharge node, resulting in high-speed operation. The conditional-discharging operation minimizes the redundant transitions of precharge nodes, resulting in low-power operation. Linear feedback shift register (LFSR) designed in a $0.18{\mu}m$ CMOS technology using the proposed flip-flop achieves 32% power reduction as compared to conventional design.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.60 no.3
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• pp.133-137
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• 2011

The purpose of smart grid is the low $CO_2$ through expansion of renewable energy. To achieve the purpose of smart grid, typical radial power distribution system will be changed to loop power distribution system. The loop power distribution system have many advantages such as low power loss, low voltage drop, and increase of connection of renewable energy. In this paper, the algorithm for minimization of interrupted section of power distribution system is proposed through communication between circuit breaker and recloser in loop power distribution system. The proposed algorithm is proved through case studies about reliability evaluation

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.391-396
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• 2005

In this dissertation, we discuss the trends of policy and analyze the technical regulation for the extremely low power devices in other countries. In addition, this paper proposes a draft revision of technical regulation for new efficient electric field strength of extremely low power devices in accordance with the technical requirement of Electromagnetic Compatibility. Based on these researches, the contents of this study will be useful to contribute a domestic efficient expansion and development of extremely low power devices and strengthen a competitiveness on international communication markets.

• Transactions on Semiconductor Engineering
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• v.2 no.1
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• pp.9-16
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• 2024

This paper discusses the design of bio-implanted ultra-low-power MICS RF transceivers for wireless sensor networks. The 400 MHz MICS standard was considered for the implementation of the WBAN wireless sensor system, indirectly minimizing radio propagation losses in the human body and the inference with surrounding networks. This paper includes link budget, various transmission and reception architectures for a system design and ultra-low power transceiver circuit techniques for the implementation of RF transceivers that meet MICS standards.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.228-230
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• 2002

We present a new low power scan testing and test data compression method for System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.4
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• pp.792-797
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• 2005

Lighting control switches based on the power line communication technology are developed and extended to incorporate dimming control to provide energy saving and appropriate illumination. The developed switch uses a general purpose microprocessor and associated electronics. Both the power line communication and the dimming function are implemented in one microprocessor, and it enables the low price commercialization. The frequency of the carrier was set at 250kHz considering the transmission data length and signal attenuation in power lines. Tests on prototypes in an low-voltage power lines have shown that the switches have a robust operation characteristics with the length of power lines and the variation of load capacities.

• The Journal of the Korea institute of electronic communication sciences
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• v.2 no.3
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• pp.163-167
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• 2007

In this paper, to design 8 bit RISC Microprocessor, a method of Clock Gating to reduce electric power consumption is proposed. In order to examine the priority, the comparison results of between a 8 bit Microprocessor which is not considered Low Power consumption and which is considered Low Power consumption using a methods of Clock Gating are represented. Within the a few periods, the results of comparing with a Microprocessor not considered the utilization of Clock Gating shows that the reduction of dynamic dissipation is minimized up to 21.56%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.59-67
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• 2007

This paper presents a low power dual-level low voltage differential signaling (DLVDS) technique using current source switching for LCD driver ICs in portable products. The transmitter makes dual level signal that has two different level signal 400mVpp and 250mVpp while keeping the advantages of LVDS. The decoding circuit recovers the primary signal from DLVDS. The low power DLVDS is implemented using a $0.25{\mu}m$ CMOS process under 2.5V supply. The proposed circuit shows 800Mbps/2-line data rate and 9mW, 11.5mW power consumptions in transmitter and receiver, respectively. The proposed DLVDS scheme reduce power consumption dramatically compare with conventional one.

• Journal of Navigation and Port Research
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• v.36 no.3
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• pp.169-173
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• 2012

In this paper, we propose an equalizer to minimize the inter-symbol interference when PSSK(Phase Silence Shift Keying) technique is applied to the low power underwater acoustic communication. PSSK is a QPSK(Quadrature Phase Shift Keying) modulation combined with PPM(Pulse Position Modulation), and it was proposed for low power communication. However, it has poor performance due to delay spread of underwater channel. In this paper, we propose a decision feedback equalizer to minimize the error in PSSK receiver. The sea trial was performed to evaluate the performance of the proposed method. In the result, the BER of PSSK was $4.36{\times}10^{-2}$ before the equalizer was applied, but the BER of PSSK was $3.95{\times}10^{-4}$ after the proposed equalizer was applied.