• Journal of Digital Contents Society
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• v.14 no.1
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• pp.59-64
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• 2013

In this paper, we proposed low power algorithm for a task. The task means the inside of a necessary processor and external resources to work accomplishment of a system. Each task analyzes a life time and a number of called for implement a low power circuit. First of all, reduce power consumption of a task have maximum power consumption for low power circuit implementation. Therefore, first selecting a task had maximum power consumption. The task had a maximum power consumption ranking consider a life time and a number of called for each task. While a life time of task is long, top priority ranking to decrease power consumption to the task that the number of call generates the power consumption how a disguise is large in case of a lot of task becomes. Frequency decision to have minimum power consumption, and decrease power consumption all the circuit by a change of frequency of the task which the minimum task that a wasting past record is the maximum becomes. Also, keep continuously minimum power consumption, with every effort task until last life time in opening life time, and decrease gets total power consumption. Experiments results show reduction in the power consumption by 5.43% comparing with that [7] algorithm.

• The Journal of the Korea Contents Association
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• v.10 no.12
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• pp.10-17
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• 2010

In this paper, we design digital D-PHY link chip controling DSI (Display Serial Interface) that meets MIPI (Mobile Industry Processor Interface) standard. The D-PHY supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions. For low power consumption, the unit blocks in digital D-PHY are optionally switched using the clock gating technique. The proposed low power digital D-PHY is simulated and compared with conven tional one about power consumption on each transaction mode. As a result, power consumptions of TX, RX, and total in HS mode decrease 74%, 31%, and 50%, respectively. In LP mode, power reduction rates of TX, RX, and total are 79%, 40%, and 51.5%, separately. We implemented the low power MIPI D-PHY digital chip using $0.13-{\mu}m$ CMOS process under 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.7
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• pp.128-134
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• 2010

In this paper, a high-power 20-way stripline power divider with low insertion loss and low side lobe level is successfully designed, fabricated and measured as a feed network for an S-band linear array antenna having Dolph-Chebyshev current distribution which has a narrow beam width and very low side lobe level (SLL). The 20-way stripline power divider consists of an 8-way power divider, three 4-way power dividers and three ring hybrids. It utilizes a T-junction structure as a basic element for power dividing. Notches and modified input/output N-to-stripline transitions are used for improving insertion loss and return loss. The fabricated power divider shows insertion loss less than 0.3 ㏈ and rms phase mismatch less than 8o in the full bandwidth. A final 40-way power divider is synthesized by combining symmetrically two 20-way power dividers and is expected to have SLL over 40 dB, based on the measured results of the 20-way power divider.

• Tribology and Lubricants
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• v.21 no.6
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• pp.249-255
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• 2005

In this paper, the friction characteristic of engine bearings has been analyzed in terms of a friction loss power, a minimum film thickness and an oil film pressure. This analysis has been focused on the fuel economy improvement with a low viscosity engine oil such as SAE 0W-40, which is used for a friction loss reduction and increased for a Diesel fuel economy. The friction loss power, the minimum oil film thickness and oil film pressure distribution for plain bearings of a Diesel engine are analyzed using an AVL's EXCITE program with a conventional engine oils of SAE 5W-40 and 10W-40, and a low viscosity engine oil of SAE 0W-40. The computed results indicate that a viscosity of engine oils is closely related to the friction loss power and the decreased minimum film thickness in which is a key parameter of a load carrying capacity of an oil film pressure distribution. When the low viscosity engine oil is supplied to engine bearings, it does not affect to the formation of a minimum oil film thickness. But the friction loss power has been significantly affected by low viscosity engine oil at a low operating temperature of 0. Based on the FEM computed results, the low viscosity engine oil at a low temperature range will be an important factor for an improvement of the fuel economy improvement.

• Magazine of the Korean Society of Agricultural Engineers
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• v.34 no.4
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• pp.39-47
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• 1992

Derivation of reasonable design low flows was attempted by comparative analysis of design low flows was derived by Power and SMEMAX transformations for the normalizations of skewed distribution and by Type m extremal distribution presented in the first report of this study with annual low flows in the five watersheds of main river basins in Korea. The results were anslyzed and summarized as follows. 1.Basic statistics of annual low flows for the selected watersheds were calculated by using Power and SMEMAX transformations. 2.Power thansformation has found to be the best for the normalization of skewed distribution among others including log, square root and SMEMAX transformations. 3.Design low flows for the selected watersheds were derived by the Power and SMEMAX transformations. 4.Judging by the relative suitabilities of the Type III extremal distribution, Power and SMEMAX transformation, it was found that design low flows of all methods are closer to the observed data within 10 years of the return period and those of Power transformation can be acknowledzed as a reasonable one among others from the viewpoint of the median between values of Type m extremal distribution and SMEMAX transformation in addition to closing the observed than others over 10 years of the return period.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.4
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• pp.221-225
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• 2014

Low power RF devices, such as RFID and Zigbee, are important for ubiquitous sensing. These devices, however, are powered by portable energy sources, such as batteries, which limits their use. To mitigate this problem, this study developed RF energy harvesting with W-CDMA for a low power RF device. Diodes are required with a low turn on voltage because the diode threshold is larger than the received peak voltage of the rectifying antenna (rectenna). Therefore, a Schottky diode HSMS-286 was used. A prototype of RF energy harvesting device showed the maximum gain of 5.8dBi for the W-CDMA signal. The 16 patch antennas were manufactured with a 10 dielectric constant PTFT board. In low power RF devices, the transmitter requires a step-up voltage of 2.5~5V with up to 35 mA. To meet this requirement, the Texas Instruments TPS61220 was used as a low input voltage step-up converter. From the evaluated result, the achievable incident power of the rectenna at 926mV to operate Zigbee can be obtained within a distance of 12m.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.2
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• pp.71-77
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• 2015

Upcoming ground-breaking applications for always-on tiny interconnected devices steadily demand two-fold features of processor cores: aggressively low power consumption and enhanced performance. We propose implementation of a novel superscalar low-power processor core with a low supply voltage. The core implements intra-core low-power microarchitecture with minimal performance degradation in instruction fetch, branch prediction, scheduling, and execution units. The inter-core lockstep not only detects malfunctions during low-voltage operation but also carries out software-based recovery. The chip incorporates a pair of cores, high-speed memory, and peripheral interfaces to be implemented with a 65nm node. The processor core consumes only 24mW at 350MHz and 0.68V, resulting in power efficiency of $80{\mu}W/MHz$. The operating frequency of the core reaches 850MHz at 1.2V.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.231-233
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• 2005

For the low-power design of the mobile multimedia system architecture, this paper modeling the mobile multimedia system and analysis the power consumption profile about the whole communication environment. The mobile system model consist of air interface, RIP front-end, base-band processing module and human interface. For the result of power consumption profile analysis, the power consumption of multimedia processing is above 60% compare to the whole power consumption in mobile multimedia system. To minimize the power consumption in processing module which consumes the large power, this paper proposed the Microscopic DVS technique which applies the optimum voltage for the each multimedia frame. For the simulation result, proposed power minimization technique reduce the power consumption about 30%.

• Journal of IKEEE
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• v.22 no.2
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• pp.480-483
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• 2018

Wireless power transfer (WPT) is the technology that forces the power to transmit electromagnetic field to an electrical load through an air gap without interconnecting wires. This technology is widely used for the applications from low power smartphone to high power electric railroad. In this paper, the model of wireless power transfer circuit for the low power system is designed for a resonant frequency of 13.45 MHz. Also, a feedback WPT circuit to improve the power transfer efficiency is proposed and shown better performance than the original open WPT circuit, and the methodology for power efficiency improvement is studied as the coupling coefficient increases above 0.01, at which the split frequency is made.

• Journal of IKEEE
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• v.22 no.3
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• pp.548-557
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• 2018

In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics instead of using replica circuit delay or four-phase handshaking protocol. Isolation cell is designed to insert it between power gating domain and normal operation domain. By using self-power gating circuit, asynchronous digital watch application consumes very low power and maintains data during sleep mode. The comparison results show the proposed ASPG technique saves leakage power up to 40.47% and delay time is reduced to 71% compared to the conventional circuit.