• 디지털콘텐츠학회 논문지
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• 제14권1호
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• pp.59-64
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• 2013

본 논문에서는 태스크에 따른 저전력 알고리즘을 제안하였다. 태스크는 시스템의 작업 수행에 필요한 프로세서의 내부와 외부의 자원을 의미한다. 태스크에 따라 저전력 회로를 구현하기 위해서는 각각의 태스크에 대한 생존시간과 호출횟수를 분석한다. 회로 전체의 소모 전력을 감소하기위해서는 소모 전력이 가장 높은 태스크의 소모 전력을 우선 줄여 저전력 회로를 구현할 수 있다. 따라서 소모 전력이 최대인 태스크를 우선 선별하여야 한다. 소모 전력이 최대인 태스크는 태스크의 생존시간과 호출횟수를 고려하여 순위를 선정한다. 태스크의 생존시간이 길면서 호출횟수가 많은 태스크의 경우 가장 큰 소모 전력을 발생시키는 태스크이므로 소모 전력을 감소시킬 최우선 순위가 된다. 소모 전력이 최대인 태스크로부터 생존 시간과 호출횟수를 이용하여 저전력 회로로 구현하기 위한 주파수를 결정하여 회로 전체의 소모 전력을 감소시킨다. 또한, 생존 시작 시간에서 생존 마지막 시간까지 계속해서 최소의 소모 전력으로 태스크를 유지시켜 전체 소모 전력을 감소시킨다. 실험 결과 [7] 알고리즘에 비해 5.43%의 전력 소모가 감소된 결과를 나타내었다.

• 한국콘텐츠학회논문지
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• 제10권12호
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• pp.10-17
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• 2010

본 논문에서는 모바일 기기 신호 인터페이스용 MIPI(Mobile industry processor interface)의 D-PHY의 디지털 블록의 저전력 설계를 제안한다. MIPI는 고속 데이터 전송을 위한 HS(high-speed)모드와 주로 제어에 사용되는 LP(low-power)모드의 두 가지 동작 모드를 갖는다. 저전력 소모를 위해 디지털 블록 내부 구성요소를 각 동작에 따라 선택적으로 스위칭 할 수 있는 클럭 게이팅(Clock gating) 기법을 적용했다. 저전력 동작의 설계에 대한 동작을 시뮬레이션을 통해 검증하고 기존의 일반적인 MIPI D-PHY 디지털 블록과 전력소모를 비교했다. HS 모드 데이터 전송동작에 대해서는 저전력 설계를 통하여 전력소모가 송신단(TX: transmitter)과 수신단(RX: receiver) 각각 74%와 31% 감소하여 전체적으로 전력소모가 50%로 줄었고, LP 모드 동작에 대해서도 전력소모가 TX와 RX 각각 79%와 40% 감소하여 전체적으로 51.5% 줄어들었다. 제안된 저전력 MIPI D-PHY 디지털 칩은 $0.13{\mu}m$ CMOS 공정에서 1.2V의 전원을 갖도록 설계 및 제작되었다.

• 대한전자공학회논문지TC
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• 제47권7호
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• pp.128-134
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• 2010

본 논문에서는 저부엽과 저손실 특성을 갖는 고전력 20-출력 스트립라인 전력분배기를 설계, 제작하고 측정하였다. 20-출력전력분배기는 S 대역 선형 배열 안테나의 급전회로를 위해 설계되었으며, 좁은 빔폭과 매우 낮은 저부엽 특성을 위해 Dolph-Chebyshev 전류 분포를 활용하였다. 20-출력 전력분배기는 8-출력 분배기 1개, 4-출력 분배기 3개와 링 하이브리드 전력분배기 3개로 구성되었으며, 전력분배의 기본적인 구조로는 T-접합 분배 구조를 사용하였다. 삽입손실과 반사손실을 개선하기 위해서 노치를 T-접합 분배 구조에 적용하였으며 N형 커넥터와 스트립라인 사이의 천이구조를 수정하였다. 설계, 제작된 전력분배기는 대역 내에서 약 0.3 dB의 삽입손실과 8o 보다 작은 rms 위상 부정합 특성을 보였다. 20-출력 전력분배기 2개를 대칭적으로 구성할 경우 40 dB 이상의 저부엽 특성 결과를 20-출력 전력분배기 측정 결과로부터 합성할 수 있었다.

• Tribology and Lubricants
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• 제21권6호
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• pp.249-255
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• 2005

In this paper, the friction characteristic of engine bearings has been analyzed in terms of a friction loss power, a minimum film thickness and an oil film pressure. This analysis has been focused on the fuel economy improvement with a low viscosity engine oil such as SAE 0W-40, which is used for a friction loss reduction and increased for a Diesel fuel economy. The friction loss power, the minimum oil film thickness and oil film pressure distribution for plain bearings of a Diesel engine are analyzed using an AVL's EXCITE program with a conventional engine oils of SAE 5W-40 and 10W-40, and a low viscosity engine oil of SAE 0W-40. The computed results indicate that a viscosity of engine oils is closely related to the friction loss power and the decreased minimum film thickness in which is a key parameter of a load carrying capacity of an oil film pressure distribution. When the low viscosity engine oil is supplied to engine bearings, it does not affect to the formation of a minimum oil film thickness. But the friction loss power has been significantly affected by low viscosity engine oil at a low operating temperature of 0. Based on the FEM computed results, the low viscosity engine oil at a low temperature range will be an important factor for an improvement of the fuel economy improvement.

• 한국농공학회지
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• 제34권4호
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• pp.39-47
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• 1992

Derivation of reasonable design low flows was attempted by comparative analysis of design low flows was derived by Power and SMEMAX transformations for the normalizations of skewed distribution and by Type m extremal distribution presented in the first report of this study with annual low flows in the five watersheds of main river basins in Korea. The results were anslyzed and summarized as follows. 1.Basic statistics of annual low flows for the selected watersheds were calculated by using Power and SMEMAX transformations. 2.Power thansformation has found to be the best for the normalization of skewed distribution among others including log, square root and SMEMAX transformations. 3.Design low flows for the selected watersheds were derived by the Power and SMEMAX transformations. 4.Judging by the relative suitabilities of the Type III extremal distribution, Power and SMEMAX transformation, it was found that design low flows of all methods are closer to the observed data within 10 years of the return period and those of Power transformation can be acknowledzed as a reasonable one among others from the viewpoint of the median between values of Type m extremal distribution and SMEMAX transformation in addition to closing the observed than others over 10 years of the return period.

• IEIE Transactions on Smart Processing and Computing
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• 제3권4호
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• pp.221-225
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• 2014

Low power RF devices, such as RFID and Zigbee, are important for ubiquitous sensing. These devices, however, are powered by portable energy sources, such as batteries, which limits their use. To mitigate this problem, this study developed RF energy harvesting with W-CDMA for a low power RF device. Diodes are required with a low turn on voltage because the diode threshold is larger than the received peak voltage of the rectifying antenna (rectenna). Therefore, a Schottky diode HSMS-286 was used. A prototype of RF energy harvesting device showed the maximum gain of 5.8dBi for the W-CDMA signal. The 16 patch antennas were manufactured with a 10 dielectric constant PTFT board. In low power RF devices, the transmitter requires a step-up voltage of 2.5~5V with up to 35 mA. To meet this requirement, the Texas Instruments TPS61220 was used as a low input voltage step-up converter. From the evaluated result, the achievable incident power of the rectenna at 926mV to operate Zigbee can be obtained within a distance of 12m.

• IEIE Transactions on Smart Processing and Computing
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• 제4권2호
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• pp.71-77
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• 2015

Upcoming ground-breaking applications for always-on tiny interconnected devices steadily demand two-fold features of processor cores: aggressively low power consumption and enhanced performance. We propose implementation of a novel superscalar low-power processor core with a low supply voltage. The core implements intra-core low-power microarchitecture with minimal performance degradation in instruction fetch, branch prediction, scheduling, and execution units. The inter-core lockstep not only detects malfunctions during low-voltage operation but also carries out software-based recovery. The chip incorporates a pair of cores, high-speed memory, and peripheral interfaces to be implemented with a 65nm node. The processor core consumes only 24mW at 350MHz and 0.68V, resulting in power efficiency of $80{\mu}W/MHz$. The operating frequency of the core reaches 850MHz at 1.2V.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 학술대회 논문집 정보 및 제어부문
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• pp.231-233
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• 2005

For the low-power design of the mobile multimedia system architecture, this paper modeling the mobile multimedia system and analysis the power consumption profile about the whole communication environment. The mobile system model consist of air interface, RIP front-end, base-band processing module and human interface. For the result of power consumption profile analysis, the power consumption of multimedia processing is above 60% compare to the whole power consumption in mobile multimedia system. To minimize the power consumption in processing module which consumes the large power, this paper proposed the Microscopic DVS technique which applies the optimum voltage for the each multimedia frame. For the simulation result, proposed power minimization technique reduce the power consumption about 30%.

• 전기전자학회논문지
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• 제22권2호
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• pp.480-483
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• 2018

Wireless power transfer (WPT) is the technology that forces the power to transmit electromagnetic field to an electrical load through an air gap without interconnecting wires. This technology is widely used for the applications from low power smartphone to high power electric railroad. In this paper, the model of wireless power transfer circuit for the low power system is designed for a resonant frequency of 13.45 MHz. Also, a feedback WPT circuit to improve the power transfer efficiency is proposed and shown better performance than the original open WPT circuit, and the methodology for power efficiency improvement is studied as the coupling coefficient increases above 0.01, at which the split frequency is made.

• 전기전자학회논문지
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• 제22권3호
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• pp.548-557
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• 2018

In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics instead of using replica circuit delay or four-phase handshaking protocol. Isolation cell is designed to insert it between power gating domain and normal operation domain. By using self-power gating circuit, asynchronous digital watch application consumes very low power and maintains data during sleep mode. The comparison results show the proposed ASPG technique saves leakage power up to 40.47% and delay time is reduced to 71% compared to the conventional circuit.