• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• ETRI Journal
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• v.26 no.3
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• pp.229-240
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• 2004

This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order onchip filters. The chip is fabricated on a $6.5-mm^{2}$ die using a standard $0.25-{\mu}m$ CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of -5 dBm, and a sensitivity of -77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive ${\pi}/4-diffrential$ quadrature phase-shift keying $({\pi}/4-DQPSK)$ mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.6
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• pp.854-862
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• 1993

All of the CMOS analog and analog-digital systems have composed with several basic circuits, and among them, a important block, the amplifier part can affect the system's performance, Therefore, according to the uses in the system, the amplifier circuit have designed as various architectures (high-gain, low-noise, high-speed circuit, etc...). In this paper, we have proposed a new CMOS differential amplifier circuit. This circuit is differential to single ended input stage comprised of CMOS complementary gain circuits having internally biasing configurations. These architectures can be achieved the high gain and reduced the transistors for biasing. As a results of SPICE simulation with the standard $1.5{\mu}m$ processing parameter, the gain of the proposed circuit have a doubly value of the typical circuit's while maintaining other characteristics(phase margin, offset, etc...). And the proposed circuit is applicated in a simple CMOS comparator which has the settling time in 7nsec(CL=1pF) and the igh output swing $({\pm}4.5V)$.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.335-338
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• 2004

We suggest Q-band MEMS MIMIC (Millimeter wave Monolithic Integrated Circuit) HEMT Oscillator using DAML (Dielectric-supported Airgapped Mcrostrip Line) structure. We elevated the signal lines from the substrate using dielectric post, in order to reduce the substrate dielectric loss and obtain low losses at millimeter-wave frequency. These DAML are composed with heist of $10\;{\mu}m$ and post size with $20\;{\mu}m\;{\times}\;20\;{\mu}m$. The MEMS oscillator was successfully integrated by the process of $0.1\;{\mu}m$ GaAs PHEMTs, CPW transmission line and DAML. The phase noise characteristic of the MEMS oscillator was improved more than 7.5 dBc/Hz at a 1 MHz offset frequency than that of the CPW oscillator And the high output power of 7.5 dBm was measured at 34.4 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.423-429
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• 2007

The clock recovery module of gap filler for satellite DMB is proposed. Proposed module sustains the output frequency of 10 MHz whether the received signal from the satellite is unstable or cut off within 0.5 sec. The advantages of this module is without frequency tuning at regular interval and low material cost. This module is fabricated by using CPLD as clock recovery IC and new type of loop filter for satisfying the fast lock time and long hold over time simultaneously. The measured performance of the fabricated module has a holdover time of 11 sec at frequency stability less than 0.01 ppm, and phase noise of -113 dBc/Hz at 100 Hz offset.

• Journal of Broadcast Engineering
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• v.16 no.6
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• pp.1026-1035
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• 2011

This paper presents generalization and application for the conventional SISO decoding algorithm of Block Turbo Codes. R. M. Pyndiah suggested an iterative SISO decoding algorithm for Product Codes, two-dimensionally combined linear block codes, on AWGN channel. It wascalled Block Turbo Codes. Based on decision of Chase algorithm which is SIHO decoding method, SISO decoder for BTC computes soft decision information and transfers the information to next decoder for iterative decoding. Block Turbo Codes show Shannon limit approaching performance with a little iteration at high code rate on AWGN channel. In this paper we generalize the conventional decoding algorithm of Block Turbo Codes, under BPSK modulation and AWGN channel transmission assumption, to the LLR value based algorithm and suggest an application example such as concatenated structure of LDPC codes and Block Turbo Codes.

• Journal of the Korean Society for Nondestructive Testing
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• v.22 no.4
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• pp.393-401
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• 2002

Pipelines in power plants, nuclear facilities and chemical industries are often affected by corrosion effects. It is important to inspect the internal defects in pipelines in oder to guarantee safe operational condition. We have taken relatively much time, cost and manpower to use conventional NDT methods because these methods are contact measuring methods. In this paper, we used digital shearography, a laser-based optical method which allows full-field measurement of surface displacement derivatives. This method has many advantages in practical use, such as low sensitivity to environmental noise, simple optical configuration and real time measurement. The experiment was performed with pressure vessels which has different internal cracks and detected internal cracks in the pressure vessels at a real time using phase shifting method.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.5
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• pp.565-570
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• 2015

Spread spectrum communications have increased interest due to their immunity to channel fading and low probability of intercept. One of the limitations of the traditional digital spread spectrum systems is the need for spreading code synchronization. Chaotic communication is the analogue alternative of digital spread spectrum systems beside some extra features like simple transceiver structures. In this paper, This paper was used instead of the digital modulation and demodulation carriers for use in the chaotic signal in a digital communication system among the chaotic modulation schemes, the Differential Chaos Shift Keying(DCSK) is the most efficient one because its demodulator detects the data without the need to chaotic signal phase recovery. Also Implementation of Differential Chaos Shift Keying Communication System Using Matlab/Simulink and the receiver con decode the binary information sent by the transmitter, performance curves of DCSK are given in terms of bit-error probability versus signal to noise ratio with spreading factor as a parameter and we compare it to BPSK modulation.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.7
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• pp.761-766
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• 2014

This study performs the analytical investigation of the oscillation voltages at the tanks of the series tuned varactor incorporating balanced common-drain, and common-gate Colpitts VCO which are able to work even at the sub-1V power supply voltages. The results the investigation predicts is verified by the simulation on the circuit behaviors of the two VCOs. The analytical investigation finds that the series tuned varactor incorporating balanced common-gate VCO generates greater oscillation voltage at the tank than the series tuned varactor incorporating balanced common-drain VCO does, which in turn is more suitable for generating the low phase noise oscillation signal from the sub-1V supply voltage than the series tuned varactor incorporating balanced common-drain VCO.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.17 no.6
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• pp.130-137
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• 2003

Because of falling-off in power quality by harmonics, obstacles like lowering of capability, noise, vibration of power facilities and so on are occurred. Also generation of harmonics is inevitable and the point at harmonics is seriously gathering strength because energy saving installation using semiconductor circuit as countermeasures to enhance energy efficiency will be broadly spread and the use of energy conversion equipment like motor speed control contrivance, energy keeping installation and so on will increase, in the future. In order to eliminate harmonics obstacle, precision measurement and analysis on voltage, current, power factor, the each ingredient of harmonic order, the percentage of total harmonic distortion, and so forth are needed. In this paper, we developed low-cost measurement system to measure and analyze power quality connected with harmonics and verified it's performance by measuring and analyzing power quality in the three-phase and four-wire system.