• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.31-40
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• 2010

This paper describes a LDPC decoder for IEEE 802.11n wireless LAN standard. The designed processor supports parity check matrix for block length of 1,944 and code rate of 1/2 in IEEE 802.11n standard. To reduce hardware complexity, the min-sum algorithm and layered decoding architecture are adopted. A novel memory reduction technique suitable for min-sum algorithm was devised, and our design reduces memory size to 25% of conventional method. The LDPC decoder processor synthesized with a $0.35-{\mu}m$ CMOS cell library has 200,400 gates and memory of 19,400 bits, and the estimated throughput is about 135 Mbps at 80 MHz@2.5v. The designed processor is verified by FPGA implementation and BER evaluation to validate the usefulness as a LDPC decoder.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.189-195
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• 2008

The OFDMA Physical layer in the WiMAX standard of IEEE 802.16e adopts 114 LDPC codes with various code rates and block sizes as a channel coding scheme to meet varying channel environments and different requirements for transmission performance. In this paper, the performances of the LDPC codes are evaluated according to various code rates and block-lengths throueh simulation studies using min-sum decoding algorithm in AWGN chamois. As the block-length increases and the code rate decreases, the BER performance improves. In the cases with code rates of 2/3 and 3/4, where two different codes ate specified for each code rate, the codes with code rates of 2/3A and 3/4B outperform those of 2/3B and 3/4A, respectively. Through the statistical analyses of the number of decoding iterations the decoding complexity and the word error rates of LDPC codes are estimated. The results can be used to trade-off between the performance and the complexity in designs of LDPC decoders.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.10C
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• pp.936-941
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• 2003

Density evolution was developed as a method for computing the capacity of low-density parity-check(LDPC) codes under the sum-product algorithm [1]. Based on the assumption that the passed messages on the belief propagation model can be approximated well by Gaussian random variables, a modified and simplified version of density evolution technique was introduced in [2]. Recently, the min-sum algorithm was applied to the density evolution of LDPC codes as an alternative decoding algorithm in [3]. Next question is how the min-sum algorithm is combined with a Gaussian approximation. In this paper, the capacity of various rate LDPC codes is obtained using the min-sum algorithm combined with the Gaussian approximation, which gives a simplest way of LDPC code analysis. Unlike the sum-product algorithm, the symmetry condition [4] is not maintained in the min-sum algorithm. Therefore, the variance as well as the mean of Gaussian distribution are recursively computed in this analysis. It is also shown that the min-sum threshold under a gaussian approximation is well matched to the simulation results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.4
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• pp.659-665
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• 2015

Recent studies on network coding scheme for increasing transmission efficiency of the network has been actively conducted. In this paper, we apply RLNC in sub-packet unit and propose a joint scheme of sub-packet level network coding and LDPC code. The proposed method can have similar ability of network coding and obtain further error correction capability. The simulation results show that the proposed one enhances error correction capability compared to the case using only LDPC when extra packets are received.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.9
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• pp.1654-1665
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• 2008

This paper presents bit splitting methods to apply multilevel modulation to iterative codes such as turbo code, low density parity check code and turbo product code. Log-likelihood ratio method splits multilevel symbols to soft decision symbols using the received in-phase and quadrature component based on Gaussian approximation. However it is too complicate to calculate and to implement hardware due to exponential and logarithm calculation. Therefore this paper presents Euclidean, MAX, sector and center focusing method to reduce the high complexity of LLR method. Also, this paper proposes optimal soft symbol split method for three kind of iterative codes. Futhermore, 16-APSK modulator method with double ring structure for applying DVB-S2 system and 16-QAM modulator method with lattice structure for T-DMB system are also analyzed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.10C
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• pp.923-929
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• 2003

Turbo processing have been known as methods close to Shannon limit in the aspect of wireless multi-input multi-output (MIMO) communications similarly to wireless single antenna communication. The iterative processing can maximize the mutual effect of coding and interference cancellation, but LDPC coding has not been used for turbo processing because of the inherent decoding process delay. This paper suggests a LDPC coded MIMO system with turbo parallel space-time (Turbo-PAST) processing for high-speed wireless communications and proposes a average soft-output syndrome (ASS) check scheme at low signal to noise ratio (SNR) for the Turbo-PAST system to decide the reliability of decoded frame. Simulation results show that the suggested system outperforms conventional system and the proposed ASS scheme effectively reduces the amount of turbo processing iterations without performance degradation from the point of average number of iterations.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.486-489
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• 2010

This paper describes a layered LDPC decoder which supports block length of 1,944 bits and code rate 1/2 for IEEE 802.11n WLAN standard. To reduce the hardware complexity, the min-sum algorithm and layered architecture is adopted. A novel memory reduction technique suitable for min-sum algorithm reduces memory size by 75% compared with conventional method. The designed processor has 200,400 gates and 19,400 bits memory, and it is verified by FPGA implementation. The estimated throughput is about 200 Mbps at 120 MHz clock by using Xilinx Virtex-4 FPGA device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.419-426
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• 2014

This paper proposes a high-throughput encoding process and encoder architecture for quasi-cyclic low-density parity-check codes in IEEE 802.11ac standard. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoding throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. In IEEE 802.11ac systems, the proposed encoder is rate compatible to support various code rates and codeword block lengths. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1248-1255
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• 2012

LDPC decoder architectures are generally classified into serial, parallel and partially parallel architectures. Conventional method of LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. It is necessary to reduce the iteration numbers and computation operations without performance degradation. This paper studies horizontal shuffle scheduling(HSS) algorithm and self-correction normalized min-sum(SC-NMS) algorithm. In the result, number of iteration is half than conventional algorithm and performance is almost same between sum-product(SP) and SC-NMS. Finally, This paper implements high-speed LDPC decoder based on FPGA. Decoding throughput is 816 Mbps.

• Journal of Navigation and Port Research
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• v.36 no.8
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• pp.631-635
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• 2012

Underwater acoustic communication has multipath error because of reflection by sea-level and sea-bottom. The multipath of underwater channel causes signal distortion and error floor. In this paper, in order to design an efficient packet structure, we employ channel coding scheme and phase recovery algorithm. For channel coding scheme, half rate LDPC channel coding scheme with N=1944 and K=972 was used. Also, decision directed phase recovery was used for correcting phase offset induced by multipath. Based on these algorithms, we propose length of data for optimal packet structure in the environment of oceanic experimentation.