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http://dx.doi.org/10.5515/KJKIEES.2012.23.11.1248

A FPGA Design of High Speed LDPC Decoder Based on HSS  

Kim, Min-Hyuk (Department of Radio Communication Engineering, Korea Maritime University)
Park, Tae-Doo (Department of Radio Communication Engineering, Korea Maritime University)
Jung, Ji-Won (Department of Radio Communication Engineering, Korea Maritime University)
Publication Information
Abstract
LDPC decoder architectures are generally classified into serial, parallel and partially parallel architectures. Conventional method of LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. It is necessary to reduce the iteration numbers and computation operations without performance degradation. This paper studies horizontal shuffle scheduling(HSS) algorithm and self-correction normalized min-sum(SC-NMS) algorithm. In the result, number of iteration is half than conventional algorithm and performance is almost same between sum-product(SP) and SC-NMS. Finally, This paper implements high-speed LDPC decoder based on FPGA. Decoding throughput is 816 Mbps.
Keywords
Low Density Parity Check Code; Horizontal Shuffle Scheduling; Normalized Min Sum; Self-Correction NMS; FPGA Implementation; Decoding Throughput;
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