• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.5
• /
• pp.949-954
• /
• 2007

In this work, temperature stable frequency-to-voltage converter is proposed. In FVC circuit input frequency is converted into output voltage signal. A FLL is similar to PLL in the way that it generates an output signal which tracks an input reference signal. A PLL is built on a phase detector, a charge pump, and a low pass filter. However, FLL does not require the use of the phase detector, the charge pump and low pass filter. The FVC is designed by using $0.25{\mu}m$ CMOS process technology. From simulation results, the variation of output voltage is less than ${\pm}2%$ in the temperature range $0^{\circ}C\;to\;75^{\circ}C$ when the input frequency is from 70MHz to 140MHz.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.22 no.8
• /
• pp.1068-1075
• /
• 2018

In this paper, a novel PLL has been proposed that reduces the size of the loop filter while suppressing spur by using a VCO with two inputs. Through the stability analysis according to the operating status, the PLL is designed to operate stably after the phase fixing. The capacitor of loop filter usually occupies larger area of PLL. It is a VCO that can reduce the size of the loop filter by increasing the effective capacitance of the capacitor through the simultaneous charge and discharge operation by two charge pumps and has two signals operating in opposite phases. The settling time of set to $80{\mu}s$ approximately by using a LSI(Locking Status Indicator) indicating the phase locking status. The proposed PLL is designed using a supply voltage of 1.8V and a $0.18{\mu}m$ CMOS process.

• International Journal of Control, Automation, and Systems
• /
• v.5 no.2
• /
• pp.161-169
• /
• 2007

The PLL equivalent augmented system incorporated with state feedback is proposed in this paper. The optimal value of filter time constant of loop filter in the phase-locked loop control system and the optimal state feedback gain designed by using linear quadratic regulator approach are derived. This approach allows the PLL control system to employ the large value of the phase-frequency gain $K_d$ and voltage control oscillator gain $K_o$. In designing, the structure of phase-locked loop control system will be rearranged to be a phase-locked loop equivalent augmented system by including the structure of loop filter into the process and by considering the voltage control oscillator as an additional integrator. The designed controller consisting of state feedback gain matrix K and integral gain $k_1$ is an optimal controller. The integral gain $k_1$ related to weighting matrices q and R will be an optimal value for assigning the filter time constant of loop filter. The experimental results in controlling the second-order lag pressure process using two types of loop filters show that the system response is fast without steady-state error, the output disturbance effect rejection is fast and the tracking to step changes is good.

• Proceedings of the KIEE Conference
• /
• 2007.04a
• /
• pp.267-269
• /
• 2007

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.4
• /
• pp.811-818
• /
• 2016

A continuous fine-tuning phase locked loop with an additional negative feedback loop has been proposed. When the phase locked loop is out-of-lock, the phase locked loop has a fast locking characteristic using the continuous band-selection loop. When the phase locked loop is near in-lock, the bandwidth is narrowed with the fine loop. The additional negative feedback loop consists of a voltage controlled oscillator, a frequency voltage converter and its internal loop filter. It serves a negative feedback function to the main phase locked loop, and improves the phase noise characteristics and the stability of the proposed phase locked loop. The additional negative feedback loop makes the continuous fine-tuning loop work stably without any voltage fluctuation in the loop filter. Measurement results of the fabricated phase locked loop in $0.18{\mu}m$ CMOS process show that the phase noise is -109.6dBc/Hz at 2MHz offset from 742.8MHz carrier frequency.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.13 no.2
• /
• pp.145-151
• /
• 2008

This paper proposes the PLL method using positive sequence voltage which is estimated by full-order state observer to find an accurate phase angle under the condition of unbalanced utility voltage. The proposed method uses the full-order state observer instead of existing method(APF All Pass Filter) to find a positive sequence of a utility voltage and this proposed method improves transient response of an estimated phase angle when a three-phase utility voltage becomes unbalanced. To compare proposed method withexisting method, experiments have been done for a phase angle detection of utility voltage when a three-phase utility voltage becomes unbalanced. Their results show that transient state response of proposed method is improved.

• The Transactions of the Korean Institute of Electrical Engineers B
• /
• v.48 no.9
• /
• pp.461-466
• /
• 1999

The switched reluctance motor (SRM) would have torque ripple if not operated with an MMF waveform specified for switching angle and phase voltage. This paper describes the robustic control scheme that permits the phase torque to be flat by PLL(Phase Locked Loop) controller. In this control scheme, the locked phase signal of PLL controls the switching dwell angle and it's loop filter signal controls the switching voltage adaptively. Experimental results show that stable dynamic performance is obtained for torque and speed together with low torque ripple on the operation of variable loads.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.2
• /
• pp.339-344
• /
• 2017

A novel structure of phase locked loop (PLL) which has small size and fast locking time with Early-late detector, Duty-rate modulator, and Lock status indicator (LSI) is proposed in this paper. The area of loop filter usually occupying the larger portion of the chip is minimized using a single small capacitor. While the conventional PLL with a single capacitor loop filter cannot work stably, the proposed PLL with two charge pumps works stably because the output voltage waveform of the proposed a single capacitor loop filter is the same as the output voltage waveform of the conventional 2nd-order loop filter. The two charge pumps are controlled by the Early-late detector which detects early-late status of UP and DN signals, and Duty-rate modulator which generates a steady duty-rate signal. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• Journal of Power Electronics
• /
• v.7 no.4
• /
• pp.310-317
• /
• 2007

In this paper, an analysis and hysteretic controller design of a $3^{rd}$ order buck converter is presented. The proposed hysteretic controller consists of an inner current-loop, just like the conventional cascade control scheme, and an outer voltage-loop for load voltage regulation. Although it is possible to include an inner current loop from different branches of the converter, from the feasibility and operational point of view, the load side capacitor current would be the better choice. The addition of an inner current-loop improves the dynamic performance of the converter while preserving the robustness of the hysteretic control. The controller formulation and closed-loop converter performance analysis are validated through computer simulations. Few experimental results of the proposed converter are given and compared with the buck converter.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.12 no.1
• /
• pp.1-6
• /
• 2019

An extremely small size multi-loop phase-locked loop(PLL) keeping phase noise performances has been proposed. It has been designed to have the loop filter made of small single capacitor with multiple Frequency Voltage Converters (FVCs) because the main goal is to make the size of the proposed PLL extremely small. Multiple FVCs which are connected to voltage controlled oscillator(VCO) make multiple negative feedback loops in PLL. Those multiple negative feedback loops enable the PLL with the loop filter made of an extremely small size single capacitor operate stably. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the 1.6ps jitter and $10{\mu}s$ locking time.