• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.6
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• pp.108-117
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• 2011

Seoul metropolitan government has been operating traffic signal control system with the name of COSMOS since 2001. COSMOS uses the degrees of saturation and congestion which are calculated by installing loop detectors. At present, inductive loop detector is generally used for detecting vehicles but it is inconvenient and costly for maintenance since it is buried on the road. In addition, the estimated queue length might be influenced in case of error occurred in measuring speed, because it only uses the speed of vehicles passing by the detector. A traffic signal control algorithm which enables smooth traffic flow at intersection is proposed. The proposed algorithm assigns vehicles to the group of each lane and calculates traffic volume and congestion degree using traffic information of each group using VANETs(Vehicular Ad-hoc Networks) inter-vehicle communication. It does not demand additional devices installation such as cameras, sensors or image processing units. In this paper, the algorithm we suggest is verified for AJWT(Average Junction Waiting Time) and TQL(Total Queue Length) under single intersection model based on GLD(Green Light District) Simulator. And the result is better than Random control method and Best first control method. In case real-time control method with VANETs is generalized, this research that suggests the technology of traffic control in signalized intersections using wireless communication will be highly useful.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.359-369
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• 2020

In this paper, we proposed a charge pump (CP) circuit that has a wide operating range while reducing the current mismatch for the PLL that generates the main clock of the CMOS X-Ray detector. The operating range and current mismatch of the CP circuit are determined by the characteristics of the current source circuit for the CP circuit. The proposed CP circuit is implemented with a wide operating current mirror bias circuit to secure a wide operating range and a cascode structure with a large output resistance to reduce current mismatch. The proposed wide operating range cascode CP circuit was fabricated as a chip using a 350nm CMOS process, and current matching characteristics were measured using a source measurement unit. At this time, the power supply voltage was 3.3 V and the CP circuit current ICP = 100 ㎂. The operating range of the proposed CP circuit is △VO_Swing=2.7V, and the maximum current mismatch is 5.15 % and the maximum current deviation is 2.64 %. The proposed CP circuit has low current mismatch characteristics and can cope with a wide frequency range, so it can be applied to systems requiring various clock speed.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.4 no.2 s.7
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• pp.13-22
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• 2005

The purpose of this research is how to estimate the traffic queue length in the signal intersection accurately. The current traffic queue length algorithm in COSMOS has been using the congestion diagram which comes from the speed of an average separated vehicle - using average vehicle length and the occupancy time from loop detectors. So some errors were occurred by the speed estimation method using average vehicle lengths. And Operators had been difficult to optimize some variables for measuring the traffic queue length estimation algorithm in COSMOS. Therefore the traffic queue length estimation algorithm on the basis of the relation between distances and occupancy rates from loop detectors was developed in this thesis. This thesis had the advantage of using occupancy rates which came out from loop detectors easily and no need to optimize some variables for the established algorithm in COSMOS. And the results of testing this algorithm in some sites which had installed COSMOS system showed better results than COSMOS system's results. But it was noted that further studies which carry it out in various sites and under various cases are necessary for applying to actual intersections.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.3
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• pp.1-7
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• 2002

This paper presents a new PLL clock generator that can improve a jitter noise characteristics and acquisition process by designing a multi-PFD(Phase Frequency Detector) and an adaptive charge pump circuit. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. An advanced multi-structured PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, in which it shows an excellent functionalities in terms of the jitter noises by designing its circuit with the exact dead zone and duty cycle. Our new designed adaptive charge pump in the loop filter of a PLL can improve an acquisition characteristic by adaptively increasing of current. The Hspice simulation is done to evaluate the performance of the proposed circuit. Simulation result shows that our PLL has under 0.01ns in the dead zone, no influence from the duty cycle of input signals and under 50ns in the acquisition time. This circuit will be able to be used in develops of high-performance microprocessors and digital systems.  

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.1100-1112
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• 1998

In this paper, a novel method of minimizing the phase error is proposed. A DP-PLL system using this method is implemented and its performacnce is investigated, too. The DP-PLL system detects the phase error between reference clock and locally generated system clock. The phase difference is then reported as a PEV(Phase Error Variation), which is propoced from the delayted n-tap rising dege clock circuit with 5ns resolution in the phase detector. The algorithm is used to track the optimal DAC coefficients, which are adjusted from sample to sample in such a way as to minimize the PEV. The proposed method is found to have remarkable good potential for fast and accurate phase error tracking characteristic. The algorithm shows good performance to supress the low frequency jitter.-ending points, we design new basis functions based on the Legendre polynomial and then transform the error signals with them. When applied to synthetic images such as circles, ellipses and etc., the proposed method provides, in overall, outstanding results in respect to the transform coding gain compared with DCT and DST. And in the case when applied to natural images, the proposed method gives better image quality over DCT and comparable results with DST.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.1982-1990
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• 1994

We implemented a PLDRO(Phase Locked Dielectric Resonator Oscillator) using the concept of the feedback property of PLL(Phase Locked Loop) for Ku-band(10.95-11.70 GHz). The conventional approaches to a PLDRO design use varactor diode tuning method.. But in theis paper, the PLDRO has the advantage of the frequency sensitivity to changes in the supple voltage of the oscillating device without the frequency-variable part by varactor diode voltage-control. and uses a SPD(Sampling Phase Detector) for phase-comparision. The PLDRO is composed of the DRO phase-locked to the reference signal of UHF band by using a SPD for high frequency stability and can be available for European FSS(Fixed Satellite Service) at 10.00GHz. The PLDRO generates the output power of 8.67 dBm at 10.00 GHz and has a phase noise of -81 dBc/Hz at 10 kHz offset from carrier. The hamonic and spurious characteristics have -42.33 dBc and -65dBc respectively. This PLDRO has much better frequency stability, lower phase noise, and more economical effect for a satellite system than conventional DRO.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.1973-1981
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• 1994

A PLDRO(Phase Locked Dielectric Resonator Oscillator) in Ku-band(10.95-11.70GHz) is designed with the concept of the feedback property of PLL(Phase Locked Loop). A series feedback type DRO is developed, and VCDRO(Voltage Controlled Dielectric Resonator Oscillator) using a varactor diode as a voltage-variable capacitor is implemented to tune oscillating frequency electrically. Then, PLDRO is designed by using a SPD(Sampling Phase Detector). This PLDRO is phase-locked voltage controlled DRO to reference source(VHF band) by SPD at 10.00 GHz for European FSS(Fixed Satellite Service). The PLDRO generates output power greater than 10dBm at 10.00 GHz and has phase noise of -80 dBc/Hz at 10 KHz offset from carrier. This PLDRO achieves much better frequency stability than conventional VCDRO.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.967-973
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• 2009

In this paper, X-band satellite communication oscillator of double phase locked is implemented by constructing a couple of phased-locked loop, and then we have analyzed the phase noise of designed PLL-DRO. The designed phase-locked oscillator is consist of series feedback DRO, frequency divider, phase detector, loop filter and programmable PLL-IC. By dividing oscillation frequency of 12.6 GHz into two frequencies, it exhibits output power of 15.32 dBm at 6.3 GHz. Phase noises of implemented oscillator are -81 dBc/Hz@100Hz, -100.86 dBc/Hz@1 kHz, -111.12 dBc/Hz@10 kHz, -116 dBc/Hz@100 kHz and -140.49 dBc/Hz@1 MHz respectively. These indicate excellent stable operation of oscillator and very good phase noise characteristics.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.12
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• pp.941-947
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• 2017

This paper reports a fractional-N phase-locked-loop(PLL) frequency synthesizer that is implemented in a $0.35-{\mu}m$ standard CMOS process and generates a quadrature signal for an FRS terminal. The synthesizer consists of a voltage-controlled oscillator(VCO), a charge pump(CP), loop filter(LF), a phase frequency detector(PFD), and a frequency divider. The VCO has been designed with an LC resonant circuit to provide better phase noise and power characteristics, and the CP is designed to be able to adjust the pumping current according to the PFD output. The frequency divider has been designed by a 16-divider pre-scaler and fractional-N divider based on the third delta-sigma modulator($3^{rd}$ DSM). The LF is a third-order RC filter. The measured results show that the proposed device has a dynamic frequency range of 460~510 MHz and -3.86 dBm radio-frequency output power. The phase noise of the output signal is -94.8 dBc/Hz, and the lock-in time is $300{\mu}s$.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.25-34
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• 2000

This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.