• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.1
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• pp.42-45
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• 1986

This paper introduces novel functionally integrated logic elements which are conceptuallized for large scale integrated circuits. Efforts are made to minimize the gate size as well as to reduce the operational voltage, without sacrificing the speed performance of the gates. The process used was a rather conventional collector diffusion isolation(CDI) process. New gate structures are formed by merging several transistors of a gate in the silicon substrate. Thested elements are CML(Current Mode Logic) and EECL (Emitter-to-Emitter Coupled Logic)gates. The obtained experimental results are power-delay product of 6~11pJ and delay time/gate of 1.6~1.8 ns, confirming the possibility of these novel gate structures as a VLSI-candidate.

• The Magazine of the IEIE
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• v.37 no.8
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• pp.50-59
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• 2010

$0.18-{\mu}m$ high voltage technology 13.5V high voltage well-based symmetric EDMOS isolated by MTI was designed and fabricated. Using calibrated process and device model parameters, the characteristics of the symmetric and asymmetric EDMOS have been simulated. The asymmetric EDMOS has higher performance, better $R_{sp}$ / BVDSS figure-of-merit, short-channel immunity and smaller pitch size than the symmetric EDMOS. The asymmetric EDMOST is a good candidate for low-power and smaller source driver chips. The low voltage logic well-based EDMOS process has advantages over high voltage well-based EDMOS in process cost by eliminating the process steps of high-voltage well/drift implant, high-temperature long-time thermal steps, etc. The specific on-resistance of our well-designed logic well-based EDMOSTs is compatible with the smallest one published. TCAD simulation and measurement results show that the improved logic well-based nEDMOS has better electrical characteristics than those of the conventional one. The improved EDMOS proposed in this paper is an excellent candidate to be integrated with low voltage logic devices for high-performance low-power low-cost chips.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.7
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• pp.863-871
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• 1999

While Logic Based Expert System (LBES) has a merit of rapid and complete inference, it also has a defect of huge knowledge base. Hierarchical LBES (HLBES) replaces the assertion time inference of LBES with the multi-level logic minimization procedure, and it guarantees smaller knowledge base comparing with LBES. This paper has two contributions. The one is proposing so-called fact-minimization procedure which reduces not only the number of facts or measured events but also the size of knowledge base dramatically. The other contribution is application of HLBES and the proposed fact-minimization to the fault diagnosis of power system. The application is successfully performed in the example with the transmission system which takes 72 goals and 352 facts.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.3
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• pp.571-578
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• 2012

In this paper, we propose two main points. The first is the constraint for logic synthesis, and the second is an efficient logic synthesis method. Logic synthesis is a process to obtain the gate-level netlist from RTL (register transfer level) codes using logic mapping and optimization with the specified constraints. The result of logic synthesis is tightly dependent on constraint and logic synthesis method. Since the size and timing can be dramatically changed by these, we should precisely consider them. In this paper, we present the considering items in the process of logic synthesis by using our experience and experimental results. The proposed techniques was applied to a circuit with the hardware resource of about 650K gates. The synthesis time for the hybrid method was reduced by 47% comparing the bottom-up method and It has better timing property about slack than top-down method.

• Progress in Superconductivity
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• v.6 no.2
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• pp.104-107
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• 2005

We have developed and tested an RSFQ 4-bit Arithmetic Logic Unit (ALU) based on half adder cells and de switches. ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We have simulated the circuit by using Josephson circuit simulation tools in order to reduce the timing problem, and confirmed the correct operation of the designed ALU. We used simulation tools of $XIC^{TM},\;WRspice^{TM}$, and Julia. The fabricated 4-bit ALU circuit had a size of $\3000{\ cal}um{\times}1500{\cal}$, and the chip size was $5{\cal} mm{\times}5{\cal}mm$. The test speeds were 1000 kHz and 5 GHz. For high-speed test, we used an eye-diagram technique. Our 4-bit ALU operated correctly up to 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• ETRI Journal
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• v.45 no.6
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• pp.996-1006
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• 2023

Renewable energy is promoted massively to overcome problems that fossil fuel power plants generate. One popular renewable energy type that offers easy installation is a photovoltaic (PV) system. However, the energy harvested through a PV system is not optimal because influenced by exposure to solar irradiance in the PV module, which is constantly changing caused by weather. The maximum power point tracking (MPPT) technique was developed to maximize the energy potential harvested from the PV system. This paper presents the MPPT technique, which is operated on a new high-gain voltage DC/DC converter that has never been tested before for the MPPT technique in PV systems. Fuzzy logic (FL) was used to operate the MPPT technique on the converter. Conventional and adaptive perturb and observe (P&O) techniques based on variables step size were also used to operate the MPPT. The performance generated by the FL algorithm outperformed conventional and variable step-size P&O. It is evident that the oscillation caused by the FL algorithm is more petite than variables step-size and conventional P&O. Furthermore, FL's tracking speed algorithm for tracking MPP is twice as fast as conventional P&O.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.65-78
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• 2017

Single Event Transient has a critical impact on highly integrated logic circuits which are currently common in various commercial and consumer electronic devices. Reliability against the soft and intermittent faults will become a key metric to evaluate such complex system on chip designs. Our previous work analyzing soft errors was focused on parallelizing and optimizing error propagation procedures for individual transient faults on logic and sequential cells. In this paper, we present a new propagation technique where a fault binary decision diagram (BDD) continues to merge every new fault generated from the subsequent logic gate traversal. BDD-based transient fault analysis has been known to provide the most accurate results that consider both electrical and logical properties for the given design. However, it suffers from a limitation in storing and handling BDDs that can be increased in size and operations by the exponential order. On the other hand, the proposed method requires only a visit to each logic gate traversal and unnecessary BDDs can be removed or reduced. This results in an approximately 20-200 fold speed increase while the existing parallelized procedure is only 3-4 times faster than the baseline algorithm.

• Journal of the Korea Institute of Military Science and Technology
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• v.5 no.2
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• pp.103-115
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• 2002

This paper describes the results on the design and implementation of large capacity cable checking system using I/O buffer method. The I/O buffer module which has feedback loops with input and output buffers is designed with logic gate in the VME board and controlled by MPC860 microprocessor. So this system can check a lot of cable at the same time with less size and less processing time than that of relay matrix method with the A/D converter. The size of the I/O buffer module can be variable according to the number of cable. And any type of cable can be checked even if the pin assignment of cable is changed.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.224-227
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• 1993

In this paper, a new LMS algorithm with a variable step size (VVS LMS) is presented. The change of step size .mu. at each iteration, which increases or decreases according to the misadaptation degree, is computed by a proportional fuzzy logic controller. As a result the algorithm has very good convergence speed and low steady-state misadjustment. The norm of the cross correlation between the estimation error and input signal is used. As a measure of the misadaptation degree. Simulation results are presented to compare the performance of the VSS LMS algorithm with the normalized LMS algorithm.

• Journal of Industrial Technology
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• v.13
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• pp.33-41
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• 1993

In this paper, a new LMS algorithm with a fuzzy variable step size (FVS LMS) is presented. The change of step size ${\mu}$, at each iteration which is increases or decreases according to the misadaptation degree, is computed by a proportional fuzzy logic controller. As a result the algorithm has very good convergence speed and low steady-state misadjustment. As a measure of the misadaptation degree, the norm of the cross correlation between the estimation error and input signal is used. Simulation results are presented to compare the performance of the FVSS LMS algorithm with the normalized LMS algorithm.